Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-16 Thread Arnd Bergmann
On Tuesday 15 October 2013, Dinh Nguyen wrote: > This makes sense for the SD/MMC driver, but do you think I can use the > same approach for > other drivers that this system manager touches? It might not be as straightforward for every driver, but something like this should work at least for some

Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-15 Thread Dinh Nguyen
On 10/15/13 2:47 PM, Arnd Bergmann wrote: On Tuesday 15 October 2013, Dinh Nguyen wrote: 1 Create a "syscon" backend driver to control your "system manager", which lets other drivers hook into it without calling a private API. Yes, if you look at drivers/mmc/host/dw_mmc-socfpga.c that is i

Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-15 Thread Arnd Bergmann
On Tuesday 15 October 2013, Dinh Nguyen wrote: > > > > 1 Create a "syscon" backend driver to control your "system manager", which > >lets other drivers hook into it without calling a private API. > Yes, if you look at drivers/mmc/host/dw_mmc-socfpga.c that is in the > mainline, > it is hooking

Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-15 Thread Dinh Nguyen
Hi Arnd, On 10/15/13 2:01 PM, Arnd Bergmann wrote: On Tuesday 15 October 2013, Dinh Nguyen wrote: Hi Arnd, On 10/15/13 7:50 AM, Arnd Bergmann wrote: On Monday 14 October 2013, dingu...@altera.com wrote: +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel) +{ + u32 hs_t

Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-15 Thread Arnd Bergmann
On Tuesday 15 October 2013, Dinh Nguyen wrote: > Hi Arnd, > > On 10/15/13 7:50 AM, Arnd Bergmann wrote: > > On Monday 14 October 2013, dingu...@altera.com wrote: > >> +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel) > >> +{ > >> + u32 hs_timing; > >> + > >> + hs_ti

Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-15 Thread Dinh Nguyen
Hi Arnd, On 10/15/13 7:50 AM, Arnd Bergmann wrote: On Monday 14 October 2013, dingu...@altera.com wrote: +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel) +{ + u32 hs_timing; + + hs_timing = SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel); + writel(hs_timing, sys_ma

Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-15 Thread Arnd Bergmann
On Monday 14 October 2013, dingu...@altera.com wrote: > +void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(u32 drvsel, u32 smplsel) > +{ > + u32 hs_timing; > + > + hs_timing = SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel); > + writel(hs_timing, sys_manager_base_addr + > SYSMGR_SDMMCGRP_CTRL_O

Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-15 Thread Dinh Nguyen
Hi Jaehoo, On 10/15/13 1:51 AM, Jaehoon Chung wrote: Hi Dinh, On 10/15/2013 04:47 AM, dingu...@altera.com wrote: From: Dinh Nguyen Add functionality in the System Manager to set the SDR settings for the SD/MMC IP. Signed-off-by: Dinh Nguyen Cc: Pavel Machek CC: Arnd Bergmann CC: Olof Joh

Re: [RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-14 Thread Jaehoon Chung
Hi Dinh, On 10/15/2013 04:47 AM, dingu...@altera.com wrote: > From: Dinh Nguyen > > Add functionality in the System Manager to set the SDR settings for the > SD/MMC IP. > > Signed-off-by: Dinh Nguyen > Cc: Pavel Machek > CC: Arnd Bergmann > CC: Olof Johansson > Cc: Rob Herring > Cc: Pawel

[RESEND PATCHv2 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

2013-10-14 Thread dinguyen
From: Dinh Nguyen Add functionality in the System Manager to set the SDR settings for the SD/MMC IP. Signed-off-by: Dinh Nguyen Cc: Pavel Machek CC: Arnd Bergmann CC: Olof Johansson Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Stephen Warren Cc: Ian Campbell Cc: Chris Ball Cc: J