Tomi,
On 05/01/15 11:18, Tomi Valkeinen wrote:
Hi Roger,
On 14/11/14 20:09, Marc Kleine-Budde wrote:
From: Roger Quadros rog...@ti.com
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.
To add more
On Tue 2015-01-06 08:59:03, Tony Lindgren wrote:
* Pavel Machek pa...@ucw.cz [150106 00:03]:
On Mon 2015-01-05 15:02:29, Tony Lindgren wrote:
Revert ARM: dts: Disable smc91x on n900 until bootloader
dependency is removed. We've now fixed the issues that
caused problems with
On Tuesday 06 January 2015 16:47:55 Peter Hurley wrote:
On 01/06/2015 02:43 PM, Arnd Bergmann wrote:
On Tuesday 06 January 2015 09:32:02 Peter Hurley wrote:
On 01/06/2015 08:13 AM, Arnd Bergmann wrote:
On Monday 05 January 2015 22:09:45 Peter Hurley wrote:
Some arches have no need to
Hello,
On 2015-01-05 18:20, Nishanth Menon wrote:
On 13:19-20150105, Marek Szyprowski wrote:
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310
Am 06.01.2015 um 17:51 schrieb Felipe Balbi:
commit 55601c9f2467 (arm: omap: intc: switch over
to linear irq domain) introduced a regression with
SDMA legacy driver because that driver strictly depends
on INTC's IRQs starting at NR_IRQs. Aparently
irq_domain_add_linear() won't guarantee that,
On 06/01/15 04:04, Paul Walmsley wrote:
Roger, Lokesh, could you try this one instead?
It passes all the basic tests here except it does not boot on the 4460
VAR-SOM-OM - unclear why at this point - but it would be good to see if it
works on your AM4372 boards, since I don't have that
Hello,
On 2015-01-05 18:22, Nishanth Menon wrote:
On 13:19-20150105, Marek Szyprowski wrote:
From: Tomasz Figa t.f...@samsung.com
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes
From: Tomasz Figa t.f...@samsung.com
On Exynos SoCs it is necessary to resume operation of L2C early in
assembly code, because otherwise certain systems will crash. This patch
adds necessary code to non-secure resume handler.
Signed-off-by: Tomasz Figa t.f...@samsung.com
[rewrote the code
From: Tomasz Figa t.f...@samsung.com
Exynos4 SoCs equipped with an L2C-310 cache controller and running under
secure firmware require certain registers of aforementioned IP to be
accessed only from secure mode. This means that SMC calls are required
for certain register writes. To handle this, an
From: Tomasz Figa t.f...@samsung.com
Firmware on certain boards (e.g. ODROID-U3) can leave incorrect L2C prefetch
settings configured in registers leading to crashes if L2C is enabled
without overriding them. This patch introduces bindings to enable
prefetch settings to be specified from DT and
From: Tomasz Figa t.f...@samsung.com
This patch adds device tree nodes for L2 cache controller present on
Exynos4 SoCs.
Signed-off-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Kukjin Kim
From: Tomasz Figa t.f...@samsung.com
Certain implementations of secure hypervisors (namely the one found on
Samsung Exynos-based boards) do not provide access to individual L2C
registers. This makes the .write_sec()-based interface insufficient and
provoking ugly hacks.
This patch is first step
All four register for latency and filter settings cannot be written in
non-secure mode and they should go through l2c_write_sec(). More on this
can be found in CoreLink Level 2 Cache Controller L2C-310 Technical
Reference Manual, 3.2. Register summary, table 3.1. This have been checked
the TRM for
From: Tomasz Figa t.f...@samsung.com
Because certain secure hypervisor do not allow writes to individual L2C
registers, but rather expect set of parameters to be passed as argument
to secure monitor calls, there is a need to provide an interface for the
L2C driver to ask the firmware to configure
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only from secure mode.
First patch updates Omap2+
From: Tomasz Figa t.f...@samsung.com
Certain platforms (i.e. Exynos) might need to set .write_sec callback
from firmware initialization which is happenning in .init_early callback
of machine descriptor. However current code will overwrite the pointer
with whatever is present in machine
2015-01-06 5:25 GMT+09:00 Arnd Bergmann a...@arndb.de:
On Monday 05 January 2015 13:19:00 Marek Szyprowski wrote:
DT_MACHINE_START(OMAP4_DT, Generic OMAP4 (Flattened Device Tree))
+ .l2c_aux_val= OMAP_L2C_AUX_CTRL,
+ .l2c_aux_mask = 0xcf9f,
+ .l2c_write_sec =
This patch implements generic DT L2C initialisation (the one from
init_IRQ in arch/arm/kernel/irq.c) for Omap4 and AM43 platforms and
kills the SoC specific stuff in arch/arm/mach-omap2/omap4-common.c.
Signed-off-by: Marek Szyprowski m.szyprow...@samsung.com
Tested-by: Nishanth Menon n...@ti.com
On 17:42-20150107, Marc Zyngier wrote:
As for the patches, they are on top of 3.19-rc3.
Applied the 21 patches and gave a quick dry run on various boards
BASE = v3.19-rc3 + 1 uImage+dtb patch for
IRQ = v3.19-rc3 + irq series
NOTE: I am yet to dig in deeper to figure out which platform may have
* Tero Kristo t-kri...@ti.com [141216 08:22]:
Hi,
These patches move the legacy clock data for omap3 under drivers/clk/ti.
After these patches are applied, it should be possible to get rid of
clk-private.h (long pending project for Mike.)
Testing done (on top of 3.18-rc1):
* Felipe Balbi ba...@ti.com [141222 12:41]:
On Thu, Dec 04, 2014 at 09:24:39AM -0600, Felipe Balbi wrote:
From: Dave Gerlach d-gerl...@ti.com
Hook dcdc2 as the cpu0-supply.
Signed-off-by: Dave Gerlach d-gerl...@ti.com
Signed-off-by: Felipe Balbi ba...@ti.com
btw, before sending
* Felipe Balbi ba...@ti.com [141204 13:05]:
Add CPSW DT binding to beagle X15 DTS in order to
get ethernet working with this board.
Note that we're also adding sleep state which will
place all pins in mux mode 15 - which means driver
off - thus conserving power.
Signed-off-by: Nishanth
* Felipe Balbi ba...@ti.com [141204 09:09]:
Hi,
On Thu, Dec 04, 2014 at 11:04:15AM -0600, Felipe Balbi wrote:
Here's a small series of non-critical fixes and improvements
for AM437x Starter Kit DTS.
Basically I'm removing unnecessary pulls and adding explicit
pinmux for a
* Pavel Machek pa...@ucw.cz [141207 08:14]:
This fixes english in comments and removes extra empty newline.
Signed-off-by: Pavel Machek pa...@ucw.cz
Applying into omap-for-v3.20/dt thanks.
Tony
diff --git a/arch/arm/boot/dts/omap3-n900.dts
b/arch/arm/boot/dts/omap3-n900.dts
index
* Nishanth Menon n...@ti.com [141205 09:51]:
TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
a fan (such as AFB02505HHB) over J1 connector for various purposes.
Provide device tree node to enable the same.
Signed-off-by: Nishanth Menon n...@ti.com
Applying into
* Kishon Vijay Abraham I kis...@ti.com [141223 02:14]:
On Tuesday 16 December 2014 02:52 PM, Vignesh R wrote:
Since phyid is no longer used by pcie driver, this field can be dropped
from the DT.
Signed-off-by: Vignesh R vigne...@ti.com
Acked-by: Kishon Vijay Abraham I
On 15:44-20150107, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [141205 09:51]:
TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
a fan (such as AFB02505HHB) over J1 connector for various purposes.
Provide device tree node to enable the same.
Signed-off
* Lad, Prabhakar prabhakar.cse...@gmail.com [141218 08:27]:
From: Benoit Parrot bpar...@ti.com
this patch adds VPFE HWMOD data for AM43xx.
Signed-off-by: Benoit Parrot bpar...@ti.com
Signed-off-by: Darren Etheridge detheri...@ti.com
Signed-off-by: Felipe Balbi ba...@ti.com
Signed-off-by:
* Felipe Balbi ba...@ti.com [141222 14:33]:
The AM437x Industrial Development Kit (IDK) is
an application development platform targeted at
industrial communication and control applications.
It comes with a 3-phase motor driver, PROFINET,
PROFIBUS and a few other industrial communication
* Felipe Balbi ba...@ti.com [141226 11:31]:
Let this board report KEY_POWER so upper layers
can decide what to do when power button is pressed.
Signed-off-by: Felipe Balbi ba...@ti.com
Applying this one into omap-for-v3.20/dt thanks.
Tony
---
arch/arm/boot/dts/am437x-sk-evm.dts | 5
* Aaro Koskinen aaro.koski...@iki.fi [141226 12:12]:
Add twl_power for N950/N9. Start with the simplest configuration to just
enable power off.
Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi
Applying into omap-for-v3.20/dt thanks.
Tony
---
arch/arm/boot/dts/omap3-n950-n9.dtsi | 5
* Felipe Balbi ba...@ti.com [141226 12:56]:
AM437x IDK board has a User Switch which we can
program to whatever we want. Because this board
doesn't have a PMIC which can give us power button
presses, let's use this user switch as a gpio-keys
power button.
Signed-off-by: Felipe Balbi
* Dmitry Lifshitz lifsh...@compulab.co.il [141229 23:42]:
On 12/29/2014 03:06 PM, Roger Quadros wrote:
On 28/12/14 16:30, Dmitry Lifshitz wrote:
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -50,7 +50,8 @@
#include omap-gpmc-smsc911x.dtsi
* Nishanth Menon n...@ti.com [150107 16:01]:
On 15:44-20150107, Tony Lindgren wrote:
* Nishanth Menon n...@ti.com [141205 09:51]:
TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
a fan (such as AFB02505HHB) over J1 connector for various purposes.
Provide device
* Felipe Balbi ba...@ti.com [150105 09:30]:
On Mon, Jan 05, 2015 at 10:32:29AM -0600, Nishanth Menon wrote:
TPS gpio now controls a 5v 500mA TL5209 regulator which may be supply
a fan (such as AFB02505HHB) over J1 connector for various purposes.
Provide device tree node to enable the same.
* Felipe Balbi ba...@ti.com [141226 08:29]:
On Fri, Dec 26, 2014 at 08:13:49AM -0800, Tony Lindgren wrote:
* Felipe Balbi ba...@ti.com [141226 07:29]:
On Fri, Dec 26, 2014 at 03:04:00PM +0200, grygorii.stras...@linaro.org
wrote:
Tony, your call
May be it will be good
* Felipe Balbi ba...@ti.com [141226 11:31]:
Enable tps65218 power button driver by default as
a dynamically linked module so AM437x SK can report
power button presses.
Signed-off-by: Felipe Balbi ba...@ti.com
Applying this into omap-for-v3.20/defconfig thanks.
Tony
---
-20150107/omap2plus_defconfig/n900.txt#L447
https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3/omap2plus_defconfig/n900.txt#L448
I had complained originally here:
http://marc.info/?t=14194620311r=1w=2 Apologies on not following
up on the thread, got distracted.
Hmm
as follows: next-20141128 worked,
next-20141201 stopped booting and the change was new dts addition,
removing the dts addition helped next-20141201 boot as well.
Current state:
https://github.com/nmenon/kernel-test-logs/blob/next-20150107/omap2plus_defconfig/n900.txt#L447
https://github.com
next-20141201 boot as well.
Current state:
https://github.com/nmenon/kernel-test-logs/blob/next-20150107/omap2plus_defconfig/n900.txt#L447
https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3/omap2plus_defconfig/n900.txt#L448
I had complained originally here:
http://marc.info/?t
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az anti-spam / anti-virus / anti-spyware. Kérjük, kattintson az alábbi
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A kellemetlenségért elnézést.
Üdvözlettel,
WEBMAIL RENDSZERGAZDA Minden jog
-20150107/omap2plus_defconfig/n900.txt#L447
https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3/omap2plus_defconfig/n900.txt#L448
I had complained originally here:
http://marc.info/?t=14194620311r=1w=2 Apologies on not following
up on the thread, got distracted.
Hmm
On Tue, Dec 09, 2014 at 06:40:35PM +, Marc Zyngier wrote:
On 09/12/14 18:17, Nishanth Menon wrote:
On 09:53-20141209, Marc Zyngier wrote:
On 08/12/14 22:41, Nishanth Menon wrote:
Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
assume you will squash as
On 01/07/2015 05:30 AM, Marek Szyprowski wrote:
This is an updated patchset, which intends to add support for L2 cache
on Exynos4 SoCs on boards running under secure firmware, which requires
certain initialization steps to be done with help of firmware, as
selected registers are writable only
-20141201 stopped booting and the change was new dts addition,
removing the dts addition helped next-20141201 boot as well.
Current state:
https://github.com/nmenon/kernel-test-logs/blob/next-20150107/omap2plus_defconfig/n900.txt#L447
https://github.com/nmenon/kernel-test-logs/blob/v3.19-rc3
On 12:21-20141210, Nishanth Menon wrote:
On 12/09/2014 12:40 PM, Marc Zyngier wrote:
On 09/12/14 18:17, Nishanth Menon wrote:
On 09:53-20141209, Marc Zyngier wrote:
On 08/12/14 22:41, Nishanth Menon wrote:
Anyways.. The following diff[1] on top of your branch makes DRA7 work - I
On Sat, Jan 03, 2015 at 10:18:58AM +0100, Pavel Machek wrote:
On Mon 2014-12-29 11:04:48, Guenter Roeck wrote:
On Mon, Dec 29, 2014 at 07:15:56PM +0100, Pavel Machek wrote:
On Mon 2014-12-29 12:01:03, Nishanth Menon wrote:
On Mon, Dec 29, 2014 at 11:52 AM, Grazvydas Ignotas
* Tero Kristo t-kri...@ti.com [141127 07:53]:
omap2xxx_cm_get_pll_config and omap2xxx_cm_get_pll_status are not used
for anything, so remove these.
I'm picking up this one to into omap-for-v3.20/cleanup.
Regards,
Tony
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* Tero Kristo t-kri...@ti.com [141127 07:53]:
APLL clock type is no longer needed as the legacy clock support is removed.
I'm picking this patch into omap-for-v3.20/cleanup thanks.
Regards,
Tony
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* Tero Kristo t-kri...@ti.com [141127 07:53]:
There is no implementation for this anywhere, so remove it from the header
files also.
Picking up this too into omap-for-v3.20/cleanup.
Tony
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Marc,
On 1/7/2015 9:42 AM, Marc Zyngier wrote:
The gic_arch_extn hack that a number of platform use has been nagging
me for too long. It is only there for the benefit of a few platform,
and yet it impacts all GIC users. Moreover, it gives people the wrong
idea (let's use it to put some new
Hi,
On Tue, Jan 06, 2015 at 11:58:56PM +0100, Pavel Machek wrote:
On Wed 2015-01-07 00:27:17, Aaro Koskinen wrote:
On Tue, Jan 06, 2015 at 11:08:05PM +0100, Pavel Machek wrote:
On Tue 2015-01-06 22:57:30, Aaro Koskinen wrote:
Hi,
On Tue, Jan 06, 2015 at 09:50:00PM +0100, Pavel
use of regmap_read() and regmap_write() in c_can_hw_raminit_syscon()
is not safe as the RAMINIT register can be shared between different drivers
at least for TI SoCs.
To make the modification atomic we switch to using regmap_update_bits().
Signed-off-by: Roger Quadros rog...@ti.com
---
* Rickard Strandqvist rickard_strandqv...@spectrumdigital.se [141207 09:23]:
Removes some functions that are not used anywhere:
omap_hwmod_pad_route_irq() omap_hwmod_no_setup_reset()
omap_hwmod_read_hardreset() omap_hwmod_del_initiator_dep()
omap_hwmod_enable_clocks() omap_hwmod_reset()
The of_platform_populate() and of_platform_depopulate() tests
are not really being tested because of some additional trailing
semi-colons after the conditional checks on couple of selftest
macro usage. Remove them to properly run all the platform
tests.
Fixes: 851da976dc1d (of/unittest: Remove
Drivers can use of_platform_populate() to create platform devices
for children of the device main node, and a complementary API
of_platform_depopulate() is provided to delete these child devices.
Any platform_data supplied for the OF devices through auxdata lookup
data is populated directly in the
Hi Grant, Rob,
I ran into two different kernel crashes when trying to use
of_platform_depopulate()
in my out-of-tree PRU remoteproc platform driver. The crashes are seen when the
child nodes created in my driver do get supplied with some platform data
(provided
through auxdata), and have IOMEM
Drivers can use of_platform_populate() to create platform devices
for children of the device main node, and a complementary API
of_platform_depopulate() is provided to delete these child platform
devices. The of_platform_depopulate() leverages the platform API
for performing the cleanup of these
Now that all DTs have been updated, entierely drop support for
the non-DT code.
This is likely to break platforms that do not update their DT,
so print a warning at boot time.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/iomap.h | 15
arch/arm/mach-tegra/irq.c
Tegra's LIC (Legacy Interrupt Controller) has been so far only
supported as a weird extension of the GIC, which is not exactly
pretty.
The stacked irq domain framework fits this pretty well, and allows
the LIC code to be turned into a standalone irqchip. In the process,
make the driver DT aware,
This proves to be usefull with stacked domains, when the current
domain doesn't implement wake-up, but expect the parent to do so.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 16
2 files changed, 17 insertions(+)
diff
Describe the legacy interrupt controller in every tegra DTSI files,
and make it the parent of most interrupts.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/boot/dts/tegra114.dtsi | 16 +++-
arch/arm/boot/dts/tegra124.dtsi | 16 +++-
Make it look like a real interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../devicetree/bindings/arm/omap/crossbar.txt | 18 +-
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git
The only user of the so called routable domain functionnality
now being fixed, let's clean up the GIC.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 59 -
include/linux/irqchip/arm-gic.h | 6 -
2 files changed,
The gic_arch_extn hack that a number of platform use has been nagging
me for too long. It is only there for the benefit of a few platform,
and yet it impacts all GIC users. Moreover, it gives people the wrong
idea (let's use it to put some new custom hack in there...).
But now that stacked irq
The GIC is now always initialized from DT on tegra, and there is
no point in keeping non-DT init code.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/irq.c | 8
1 file changed, 8 deletions(-)
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
Support for the TI crossbar used on the DRA7 family of chips
is implemented as an ugly hack on the side of the GIC.
Converting it to stacked domains makes it slightly more
palatable, as it results in a cleanup.
Unfortunately, as the DT bindings failed to acknowledge the
fact that this is
If we detect that our DT has a LIC node, don't setup gic_arch_extn,
and skip tegra_legacy_irq_syscore_init as well.
This is only a temporary measure until that code is removed for good.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-tegra/irq.c | 11 +++
OMAP4/5 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/ti,omap4-wugen-mpu| 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
diff --git
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-zynq/common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-zynq/common.c
shmobile only uses gic_arch_extn.irq_set_wake to prevent the GIC
from returning -ENXIO when receiving a wake-up configuration request.
It is a lot simpler to tell the irq layer that we don't need any
configuration by using the IRQCHIP_SKIP_SET_WAKE, thanks to the
new gic_set_irqchip_flags
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
.../interrupt-controller/nvidia,tegra-ictlr.txt| 39 ++
1 file changed, 39 insertions(+)
create mode 100644
Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
diff --git
Document the fact that some Exynos PMUs are capable of acting as
an interrupt controller.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/samsung/pmu.txt | 13 +
1 file changed, 13 insertions(+)
diff --git
IMX6 has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does just this, updating the DT files to actually
reflect what the HW provides.
BIG FAT WARNING: because the DTs were so far lying
Nobody will regret it.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
Documentation/devicetree/bindings/arm/gic.txt | 6 --
1 file changed, 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/gic.txt
b/Documentation/devicetree/bindings/arm/gic.txt
index 8112d0c..631cb71
Instead of directly touching gic_arch_extn, which is about to
be removed, use gic_set_irqchip_flags instead.
Acked-by: Linus Walleij linus.wall...@linaro.org
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
arch/arm/mach-ux500/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Now that the users of gic_arch_extn have been fixed, drop the
feature for good. This leads to the removal of some now useless
locking.
Signed-off-by: Marc Zyngier marc.zyng...@arm.com
---
drivers/irqchip/irq-gic.c | 54 -
A common use of gic_arch_extn is to set up additional flags
to the GIC irqchip. It looks like a benign enough hack that
doesn't really require the users of that feature to be converted
to stacked domains.
Add a gic_set_irqchip_flags() function that platform code can
call instead of using the
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