as the Romans.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 18 +++---
arch/arm/mach-omap2/clock.h |1 -
arch/arm/mach-omap2/clock24xx.c |5 +++--
arch/arm/mach-omap2/clock34xx.c |4 ++--
4 files changed, 12 insertions(+), 16 deletions
[EMAIL PROTECTED] for catching some
embarrassing errors in earlier versions of this code.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/cm.h | 34 +-
arch/arm/mach-omap2/prm.h | 37 ++---
2 files changed
slightly while we
are here.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c |8 +++-
arch/arm/mach-omap2/clock24xx.c | 15 ---
arch/arm/mach-omap2/pm.c | 19 +--
arch/arm/mach-omap2/prcm.c| 14
Hello,
this patch series adds DPLL autoidle control for OMAP3. It then adds
OMAP3 DPLL enable and disable support via clock framework clk_enable()
and clk_disable(). It also updates the clock34xx.h comments to credit
frequent contributors.
I personally have verified that DPLL disable has been
Ensure that people who have contributed several bug fixes to the
34xx clock framework are appropriately credited.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.h | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
Index: linux-omap/arch/arm
.: the CORE DPLL (DPLL3) has three autoidle mode options, rather
than just two. This code currently does not support the third option,
low-power bypass autoidle.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c | 79
will go to bypass.
Otherwise, the DPLL will attempt to lock. Disabling means going
from bypass or lock to off.
Jouni Högander contributed a fix for _omap3_noncore_dpll_lock().to
bypass the DPLL state test when the DPLL is in autoidle mode.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm
Hello,
the following two patches add:
- a new DPLL rate rounding algorithm for OMAP2/3, and
- non-CORE DPLL rate programming for OMAP3 (e.g., DPLLs 1, 2, 4, 5)
The rate rounding code is not yet integrated into the OMAP2 DPLL - this
will come in future patches - but it is integrated on OMAP3.
.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 198 +-
arch/arm/mach-omap2/clock.h |5
arch/arm/mach-omap2/clock24xx.c | 12 +-
arch/arm/mach-omap2/clock24xx.h | 17 ++-
arch/arm/mach-omap2/clock34xx.h
Add OMAP2-specific powerdomains.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/powerdomains.h | 16 ++-
arch/arm/mach-omap2/powerdomains24xx.h | 176 +
arch/arm/mach-omap2/prm-regbits-24xx.h | 12 +-
3 files changed, 199
+1,296 @@
+/*
+ * OMAP34XX powerdomain definitions
+ *
+ * Copyright (C) 2007-8 Texas Instruments, Inc.
+ * Copyright (C) 2007-8 Nokia Corporation
+ *
+ * Written by Paul Walmsley
+ * Debugging and integration fixes by Jouni Högander
+ *
+ * This program is free software; you can redistribute
Hello Hiroshi,
On Thu, 17 Apr 2008, Hiroshi DOYU wrote:
debugfs can provide the infrastructure to trace the dependencies of
clock tree hierarchy quite visibly. This patch enables to keep track
of clock tree hierarchy and expose their attributes under each clock
directry as below:
As a
Hello David,
On Thu, 17 Apr 2008, David Brownell wrote:
On Thursday 17 April 2008, Paul Walmsley wrote:
But it would be nice to be able to call into clock functions like
round_rate, set_rate, and set_parent via filesystem writes for debugging
purposes, and I don't think that debugfs
Hello David,
On Thu, 17 Apr 2008, David Brownell wrote:
struct dentry *debugfs_create_file(const char *name, mode_t mode,
struct dentry *parent, void *data,
const struct file_operations *fops);
... provide a
Hello Hiroshi, David,
On Thu, 17 Apr 2008, David Brownell wrote:
On Thursday 17 April 2008, Hiroshi DOYU wrote:
And if there will be a little possibility that sysfs attribute can be
used by userland in the future, keeping sysfs instead of debugfs
doesn't seem not so illegal, does it?
Hello Igor,
On Thu, 17 Apr 2008, Igor Stoppa wrote:
On Thu, 2008-04-17 at 13:44 -0600, ext Paul Walmsley wrote:
True, but if we can do a debugfs implementation first, then that seems
like a good way to start, no? Userspace PM implementations are probably
some months in the future
Add OMAP2-specific powerdomains.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/powerdomains.h | 14 ++
arch/arm/mach-omap2/powerdomains24xx.h | 200
arch/arm/mach-omap2/prm-regbits-24xx.h | 12 +-
3 files changed, 222 insertions
:
textdata bss dec hex filename
3269405 152552 100736 3522693 35c085 vmlinux.3430sdp.orig
3272093 154920 100736 3527749 35d445 vmlinux.3430sdp
Paul Walmsley (4):
Subject: Integrate OMAP3 clocks with clockdomain code
Subject: encode OMAP2/3 clockdomains
Subject
.
The patch adds a Kconfig option, CONFIG_OMAP_DEBUG_CLOCKDOMAIN, which
when enabled will emit verbose debug messages via pr_debug().
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/Makefile|3
arch/arm/mach-omap2/clockdomain.c | 602
Add clockdomain definitions for OMAP24xx and OMAP34xx chips.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clockdomains.h| 298 +
arch/arm/mach-omap2/cm-regbits-24xx.h | 24 ++-
arch/arm/mach-omap2/cm-regbits-34xx.h | 42
use of prm_rmw_reg_bits() in
omap2_enable_osc_ck() which is changing bits in PRCM_CLKSRC_CTRL
that are unrelated to the function it is performing.
Signed-off-by: Seth Forshee [EMAIL PROTECTED]
Indeed, you have found a bug - thanks for the patch!
Acked-by: Paul Walmsley [EMAIL PROTECTED
PROTECTED]
Acked-by: Paul Walmsley [EMAIL PROTECTED]
- Paul
[EMAIL PROTECTED]
Acked-by: Paul Walmsley [EMAIL PROTECTED]
although it's less of a race issue, than it is a convenience issue for
OMAP2/3 device driver folks...
- Paul
It's springtime in the Northern Hemisphere; time for plants to flower,
students to graduate, or not, and Linux hackers to generate cleanup
patches against the source tree...
These patches fix all of the sparse warnings against the
arch/arm/mach-omap2 directory, and fix some of the checkpatch.pl
() - none of this code is particularly
fast-path code, so the performance impact seems slim; and some of those
likely() and unlikely() indicators are probably not as accurate as the
ARM's branch predictor
- removing some superfluous casts
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch
/ includes.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/gpmc.c | 42 +-
arch/arm/mach-omap2/io.c | 12 +-
arch/arm/mach-omap2/memory.h |7 ++
arch/arm/mach-omap2/sdrc.h |4
Fix sparse warnings with the OMAP2 SCM code. Involves tagging
appropriate pointer-integer type conversions with __force. Also fix
a checkpatch warning re: conversion of asm/ includes to linux/.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/control.c | 13
Fix remaining sparse warnings in arch/arm/mach-omap2/. These fixes
mostly consist of:
- tagging appropriate integer-pointer casts with __force
- marking private structures and functions as static; adding function
prototypes in .h files for public functions
- assigning NULL to pointers, not 0
Convert pwrdm_mutex to pwrdm_rwsem to avoid trying to relock mutex in the
event that the pwrdm_for_each() callback function calls something that
triggers a pwrdm_lookup(). Problem found by Jouni Högander
[EMAIL PROTECTED]
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach
Two minor OMAP3 clock framework fixes. This series:
- puts the sys_clkout2 struct clk into the core_clkdm where it belongs
- removes the omap2_noncore_dpll_set_rate() function pointer from the
DPLL3 struct clk (since DPLL3 is the CORE DPLL)
- Paul
---
arch/arm/mach-omap2/clock34xx.h |
DPLL3 is the CORE DPLL and cannot use the non-CORE set_rate function since
SDRC is downstream.
Signed-off-by: Paul Walmslsy [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.h |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/clock34xx.h
Hello Dirk,
On Sat, 10 May 2008, Dirk Behme wrote:
-- cut --
git bisect bad
757f0b4ad6b0fd4377c2ee512fc595b5778aa3ac is first bad commit
commit 757f0b4ad6b0fd4377c2ee512fc595b5778aa3ac
Author: Paul Walmsley [EMAIL PROTECTED]
Date: Fri May 9 14:45:24 2008 -0700
powerdomain
On Tue, 13 May 2008, Dirk Behme wrote:
If you like, I can recheck again. But would be better if anybody else could
confirm this, just in case I missed anything. Hint, hint ;)
I would love to help, but, no Beagle here :-(
In a private mail I got:
-- cut --
To add another data point: on
omap3_noncore_dpll_enable() calls clk_get_rate(), which causes an attempt
to re-enter the clockfw_lock spinlock. Fix by calling
omap2_get_dpll_rate() instead.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c |2 +-
1 files changed, 1 insertions(+), 1
Simplify the IRQ register/IRQ register bit calculations in
mach-omap2/irq.c.
Test-booted on 3430SDP.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
size:
textdata bss dec hex filename
3341347 170992 109008 3621347 3741e3 vmlinux.3430sdp
3341315 170992 109008
Hi Peter,
a few quick comments.
On Mon, 19 May 2008, Peter 'p2' De Schrijver wrote:
+#define SCM_CONTROL_TEMP_SENSOR (OMAP343X_SCM_BASE + 0x524)
Consider moving this to include/asm-arm/arch-omap/control.h ?
+#define CM_FCLKEN3_CORE (OMAP3430_CM_BASE + 0x200 + 0x8)
The above define
Hello Kyungmin,
On Wed, 21 May 2008, Kyungmin Park wrote:
On Wed, May 21, 2008 at 3:21 AM, Paul Walmsley [EMAIL PROTECTED] wrote:
static void omap_mask_irq(unsigned int irq)
{
- int offset = (irq 5) 5;
+ int offset = irq (~(IRQ_BITS_PER_REG - 1));
- if (irq
annotating the clock framework.
Tested on an N800 with the serial console enabled, and power
consumption matches current l-o git HEAD during screen on, dim, and off;
and DSP still works.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
--
size:
textdata bss dec hex filename
3160390
Add a function pwrdm_get_mem_bank_count() to the powerdomain code to
return the number of memory banks contained inside an OMAP
powerdomain. This will be used by the PM code to configure the memory
bank retention state.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2
This patch adds a missing OMAP24xx clock, the SSI L4 interface clock,
as ssi_l4_ick.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock24xx.h | 15 +++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch
The recent powerdomain and clockdomain layer updates for OMAP24XX should
now control the DSP powerdomain and clockdomain automatically when
DSP Gateway calls clk_{enable,disable}(). Remove the manual
clockdomain/powerdomain register tweaks from DSP Gateway.
Signed-off-by: Paul Walmsley [EMAIL
happening on the chip.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm24xx.c | 106 +-
1 files changed, 72 insertions(+), 34 deletions(-)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 787a95e..5d060de
Great - thanks everyone for the review,
- Paul
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To unsubscribe from this list: send the line unsubscribe linux-omap in
the body of a message to [EMAIL PROTECTED]
More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Tony,
On Wed, 21 May 2008, Tony Lindgren wrote:
* Paul Walmsley [EMAIL PROTECTED] [080520 18:20]:
Modify mach-omap2/irq.c to simplify the IRQ number-to-IRQ register and IRQ
number-to-register bit calculations.
How about patching Jouni's new omap_irq_pending() for this too?
done
Hello,
This patch series adds D2D (die-to-die) clockdomain handling into
OMAP3 ES2+ builds. It seems the D2D clockdomain logic is still
present on the chip and must be manually programmed to allow the
CORE_D2D clockdomain to go inactive.
For this to work, the pm34xx.c code also had to be
Hi Kevin,
On Tue, 20 May 2008, Kevin Hilman wrote:
The locking in the get_rate() hook is unnecessary, and causes problems
when used with the -rt patch, since it may be called recursively.
Signed-off-by: Kevin Hilman [EMAIL PROTECTED]
Acked-by: Paul Walmsley [EMAIL PROTECTED]
BTW, looks
Hello,
On Thu, 5 Jun 2008, Igor Stoppa wrote:
- if a dvfs change is responsible of changing the rate supplied to a
driver which asked it with clk_get_rate(), the dvfs transition has no
reason to happen in case it would violate the constraints set by clock
users.
There aren't any such
On Mon, 9 Jun 2008, Jouni Hogander wrote:
omap2_clk_wait_ready was wrongly modified to check
registers contents. This fix changes it back to check
addresses.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
Acked-by: Paul Walmsley [EMAIL PROTECTED]
- Paul
--
To unsubscribe from this list
Hello Tero,
A few minor comments based on a quick look.
In terms of the OMAP3 code, is that for retention-idle only, or does it
work with off-idle also?
On Tue, 10 Jun 2008, Tero Kristo wrote:
+const u32 omap2_uart_wk_bit[OMAP_MAX_NR_PORTS] = {
+ OMAP24XX_ST_UART1,
Hi Tero,
Let me begin by saying that I don't care too much about the 32-bit SCM
register read change; I just happen to think that it is easier to read.
That said, one comment of yours bears some additional discussion:
On Thu, 12 Jun 2008, [EMAIL PROTECTED] wrote:
Also, the spec says that
until the
Linux PM QoS layer supports these features.
This interface is a collaborative product of many people from Nokia
and TI: Karthik Dasu, Jouni Högander, Tony Lindgren, Rajendra Nayak,
Sakari Poussa, Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul
Walmsley, and Richard Woodruff.
Included
Add a default OMAP PM no-op layer, defining the interface between
device drivers, CPUFreq, and DSP Bridge on one side; and hardware-specific
APIs on the other (e.g., powerdomain API, clock framework, etc).
Copious documentation is in the omap-pm-noop.c file itself.
Signed-off-by: Paul Walmsley
Hello Russell,
On Sat, 14 Jun 2008, Russell King - ARM Linux wrote:
On Fri, Jun 06, 2008 at 06:30:53PM -0700, Tony Lindgren wrote:
omap_chip is set in mach-omap2/id.c by _set_omap_chip(). Other
code should use the omap_chip_is() function to test against omap_chip.
+/**
+ *
Hello Jouni,
On Wed, 18 Jun 2008, Högander Jouni wrote:
ext Paul Walmsley [EMAIL PROTECTED] writes:
Major changes since the first version:
1. Jouni Hogander suggested that the set_max_cpu_lat() function be
merged into set_max_dev_wakeup_lat(), when set_max_dev_wakeup_lat
This series adds a clock rate change notifier to the OMAP clock
framework. Currently only post-rate-change notification is
implemented, although pre-rate-change notification is in the works.
Clock post-rate-change notifiers are intended for drivers that need to
be notified when other code (such
if
necessary.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/plat-omap/clock.c | 118 +++-
1 files changed, 115 insertions(+), 3 deletions(-)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 421d076..354f45f 100644
--- a/arch
-linefetch (0x1028)
This patch modifies omap2_clk_wait_ready() to wait for the DSS to become
accessible after dss1_alwon_fclk is enabled.
Thanks to Anand Gadiyar [EMAIL PROTECTED] for identifying one of the
problem patches.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c
Stoppa [EMAIL PROTECTED] and Richard Woodruff
[EMAIL PROTECTED] for help with the SSI portion of the patch.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 63 +
arch/arm/mach-omap2/cm-regbits-34xx.h |4 ++
2 files
Hi Dirk,
On Sun, 22 Jun 2008, Dirk Behme wrote:
Fix warnings
Looks good, but one request: for consistency with the rest of the file,
please use:
.enable_reg = _OMAP34XX_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD,
PM_PWSTCTRL),
in usbhost_sar_fck, rather than OMAP3430_USBHOST_MOD.
-
On Sun, 22 Jun 2008, Dirk Behme wrote:
Fix warnings
One other request while you're in there: could you please also convert the
0x0070 in:
#define OMAP3430_PRM_CLKSRC_CTRL \
OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070)
to
#define
Hi Jouni
On Mon, 23 Jun 2008, Högander Jouni wrote:
Hello Paul,
It should actually wait for SSI also. Read my comments below.
...
And add this part
+ if (cpu_is_omap34xx()
+ prcm_mod == OMAP34XX_CM_REGADDR(CORE_MOD, 0)
+ clk-enable_bit ==
:229: warning: initialization makes pointer
from integer without a cast
arch/arm/mach-omap2/clock34xx.h:2238: warning: initialization makes pointer
from integer without a cast
Signed-off-by: Dirk Behme [EMAIL PROTECTED]
Thanks, Dirk.
Acked-by: Paul Walmsley [EMAIL PROTECTED]
- Paul
programming. An off-by-one error existed in
omap3_noncore_dpll_program(), causing DPLLs to be programmed with a higher
divider than intended.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c | 13 -
1 files changed, 8 insertions(+), 5 deletions
OMAP34xx ES2 TRM Delta G to H states that the divider for DPLL1_FCLK and
DPLL2_FCLK can divide by 4 in addition to dividing by 1 and 2. Encode this
into the OMAP3 clock framework.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.h | 20
Hello Jouni,
On Tue, 17 Jun 2008, Jouni Hogander wrote:
Clock path should be powered down only after all it's clients are
properly disabled. Generally we don't have working implementation for
checking wether some clock is enabled or disabled.
Just wanted to revisit this again briefly. Is
Hello Ramesh,
On Wed, 18 Jun 2008, Ramesh Gupta G wrote:
Will this interface provides information of max number if OPPs supported and
the frequency corresponding to eah OPP level?
It could be added. This is for DSPBridge use, not for the MPU, correct?
Is the idea essentially to replace
On Wed, 25 Jun 2008, Jouni Hogander wrote:
Enable bit for dpll4_m4x2_ck is OMAP3430_PWRDN_DSS1_SHIFT instead of
OMAP3430_PWRDN_CAM_SHIFT.
Signed-off-by: Jouni Hogander [EMAIL PROTECTED]
Acked-by: Paul Walmsley [EMAIL PROTECTED]
- Paul
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To unsubscribe from this list: send the line
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/powerdomain.c | 68 +++
include/asm-arm/arch-omap/powerdomain.h | 11 +
2 files changed, 79 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c
b/arch/arm/mach
code to enable and disable
automatic SAR,
- move the USBHOST SAR support from the clock fw to the powerdomain
layer,
- add support for USBTLL SAR,
- enable SAR for all powerdomains that support it upon powerdomain
initialization.
Boot-tested on 3430SDP ES2.
Signed-off-by: Paul Walmsley
flag to the ES2 powerdomain.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/powerdomains.h |3 ++-
arch/arm/mach-omap2/powerdomains34xx.h | 23 +--
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/powerdomains.h
latency is measurable, an alternate approach would be to only enable
hardware save-and-restore if there are USB devices attached.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/pm34xx.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach
Hello Jouni,
On Wed, 25 Jun 2008, Jouni Hogander wrote:
+ /* XXX Set all plls to autoidle. This is needed until autoidle is
+ * enabled by clockfw */
+ cm_write_mod_reg(1 OMAP3430_CLKTRCTRL_IVA2_SHIFT,
+ OMAP3430_IVA2_MOD,
+
, and Dirk Behme
[EMAIL PROTECTED] for review of a previous version.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 34 +
arch/arm/mach-omap2/cm-regbits-34xx.h |4 +++-
2 files changed, 33 insertions(+), 5 deletions
interface and functional
clocks are enabled.
Thanks to Igor Stoppa [EMAIL PROTECTED], Richard Woodruff
[EMAIL PROTECTED], and Jouni Högander [EMAIL PROTECTED] for
help with this portion of the patch.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 59
The test in omap2_clk_wait_ready() for DSS or CAM clocks didn't
verify that the PRCM {F,I}CLKEN1 register was in the CORE powerdomain.
Add this check in.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 10 +++---
1 files changed, 7 insertions(+), 3
pertaining to the 96MHz clocks.
From: Paul Walmsley [EMAIL PROTECTED]
The 96MHz portion of the clock tree should now have reasonable
fidelity to the 34xx TRM Rev I.
One remaining question mark: it's not clear exactly which 96MHz source
clock the USIM uses. This patch sticks with the previous
Hello Ramesh,
On Thu, 3 Jul 2008, Ramesh Gupta G wrote:
Perhaps something similar to an OMAP PM function
omap_pm_dsp_get_opp_table() that DSPBridge could call on startup?
Can you please provide tentative dates for the patches available with above
function?
DSPBridge already has all of
:
cd /debug/clock/virt_26m_ck/osc_sys_ck/sys_ck/dpll3_ck/dpll3_m2_ck
# Switch to M2 = 2 (assuming DPLL3 at 331MHz)
echo -n 165941176 rate
# Switch back to M2 = 1
echo -n 331882352 rate
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
size:
textdata bss dec
Rename arch/arm/mach-omap2/memory.c to arch/arm/mach-omap2/sdrc2xxx.c, since
it contains exclusively SDRAM-related functions. Most of the functions
are also OMAP2xxx-specific - those which are common will be separated out
in a following patch.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED
outside the sdrc2xxx.c file.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/Makefile |6 +++-
arch/arm/mach-omap2/clock24xx.c| 23 ---
arch/arm/mach-omap2/io.c |2 +
arch/arm/mach-omap2/sdrc.c | 57
().
This patch does not define the values for different memory chips, nor
does it use the values for anything; those will come in subsequent patches.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/board-2430sdp.c |2 +-
arch/arm/mach-omap2/board-3430sdp.c
Add timing data for the Qimonda HYB18M512160AF-6 SDRAM chip, used on
the OMAP3430SDP boards.
Thanks to Rajendra Nayak [EMAIL PROTECTED] for his help identifying
the chip used on 3430SDP.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/board-3430sdp.c
] for his help identifying
the chips used on Beagle OMAP3EVM.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/board-omap3beagle.c |4 +-
arch/arm/mach-omap2/board-omap3evm.c |4 +-
arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h | 55
.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/sram34xx.S |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S
index 63db781..1acdbe8 100644
--- a/arch/arm/mach-omap2/sram34xx.S
+++ b/arch/arm
The only SRAM function currently used on OMAP3 is the CORE DPLL M2 divider
reprogramming function; remove the rest of the stubs.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/sdram-micron-mt46h32m32lf-6.h |2 -
arch/arm/mach-omap2/sram34xx.S
this function for the set_rate function pointer in the dpll3_m2_ck
struct clk. With this function in place, PM/OPP code should be able to
alter SDRAM speed via code similar to:
clk_set_rate(dpll3_m2_ck, target_rate).
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.c
By the way, this last patch will need to be hand-edited to
remove the following part to apply cleanly on mainline. I'll post a
refreshed series later for merging.
- Paul
On Mon, 7 Jul 2008, Paul Walmsley wrote:
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
On Tue, 8 Jul 2008, Rajendra Nayak wrote:
From: Paul Walmsley [mailto:[EMAIL PROTECTED]
A few notes:
- The M2 divider switch does not seem to work consistently on the
3430SDP I use to test. In particular, the switch back to
M2=1 results
in a hung console.
SRAM being
On Tue, 8 Jul 2008, Woodruff, Richard wrote:
SRAM being mapped as cacheable could be a possible reason for this.
Second this.
Yeah, agreed that it needs to be done, but SRAM in CDP 12.17 is still
marked cacheable too, right? Did CORE M2 divider changes work in CDP
12.17?
Also still
Hi,
this patch allows one to set the rate of clocks without id fields from
debugfs. It also supports round_rate testing via debugfs also.
This is not for merging, at least not yet. But people out there who are
hacking on OMAP clock code may find it useful.
Here's an example:
mount -t
Hello Richard,
On Tue, 8 Jul 2008, Woodruff, Richard wrote:
If say your I2C failed to raise the voltage or you didn't program in
enough setup time into volt control you might try and go fast with out
having proper voltage yet.
Thanks for the ideas. Unfortunately, no access to an SDP with
Hello,
A quick update on the CORE DPLL M2 divider change patches; they seem to
work okay on the BeagleBoard here. (The rate tables need minor tweaks to
match the Beagle DPLL clock rates set up by u-boot.)
Not sure what's going on with the 3430SDP. I suspect there are some PRCM
register
Hello Rajendra,
On Mon, 14 Jul 2008, Rajendra Nayak wrote:
Yes, I probably was using an older omap-pm-noop patch from Paul.
I did not refresh it since, the later one sent was again not the final one.
I though I would refresh it once the final version is posted.
Paul,
Would you be posting
, rather than afterwards.
The patch has survived twenty-two reboots on the 3430SDP here without
wedging I2C1. Not absolutely dispositive, but promising!
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
drivers/i2c/busses/i2c-omap.c | 10 --
1 files changed, 8 insertions(+), 2
Högander, Tony Lindgren, Rajendra Nayak,
Sakari Poussa, Veeramanikandan Raju, Anand Sawant, Igor Stoppa, Paul
Walmsley, and Richard Woodruff.
Included in the patch is a 'no-op' implementation that documents the
interface and emits debug messages. Rajendra Nayak at TI has
developed an initial
This series fixes a few bugs in the OMAP3 clock tree. The most noticeable
difference is that the Clock usbhost_48m_fck didn't enable in 10 tries
no longer appears during boot.
---
textdata bss dec hex filename
3391587 157104 107136 3655827 37c893 vmlinux.3430sdp.orig
on usbhost_120m_fck.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock.c | 63 ++---
arch/arm/mach-omap2/cm-regbits-34xx.h |2 +
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach
setting, which
seems reasonable.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
arch/arm/mach-omap2/clock34xx.h | 60 +
arch/arm/mach-omap2/cm-regbits-34xx.h |8 +++-
2 files changed, 44 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-omap2
after
kernel init on Beagle.
Thanks to Philip Balister [EMAIL PROTECTED], Koen Kooi
[EMAIL PROTECTED], Måns Rullgård [EMAIL PROTECTED], Steve
Sakoman [EMAIL PROTECTED] and others on #beagle for help tracing
these problems.
Tested on BeagleBoard rev B4 (3530ES2.2).
- Paul
---
Paul Walmsley (9
twl_irq_init() clears PWR interrupt status bits, then masks the interrupts
off, then clears the PWR interrupt status bits again. The first clear
seems unnecessary, so, remove it.
Signed-off-by: Paul Walmsley [EMAIL PROTECTED]
---
drivers/i2c/chips/twl4030-core.c | 18 --
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