Sorry for the format. Emailing from webmail.
From: Daniel Lezcano [daniel.lezc...@linaro.org]
Sent: Wednesday, September 17, 2014 2:49 PM
To: Menon, Nishanth; Shilimkar, Santosh; Tony Lindgren; Kristo, Tero; Paul
Walmsley
Cc: Kevin Hilman; linux-arm-ker
From: Daniel Lezcano [daniel.lezc...@linaro.org]
Sent: Wednesday, September 17, 2014 8:22 PM
To: Shilimkar, Santosh; Menon, Nishanth; Tony Lindgren; Kristo, Tero; Paul
Walmsley
Cc: Kevin Hilman; linux-arm-ker...@lists.infradead.org;
linux-omap
Sorry for top posting Probably we should move the dmtimer to drivers/misc
or create drivers/timer/
This has been pending for quite some time now
Tony, what you say ?
From: linux-arm-kernel [linux-arm-kernel-boun...@lists.infradead.org] on behalf
...@linaro.org]
Sent: Sunday, July 28, 2013 10:11 AM
To: Alexander Holler
Cc: ext Tony Lindgren; Grant Likely; Shilimkar, Santosh; Kevin Hilman; Javier
Martinez Canillas; Jon Hunter; Jean-Christophe PLAGNIOL-VILLARD; Enric Balletbo
Serra; Linux-OMAP; Florian Vaussard; Aaro Koskinen; Krishnamoorthy
...@atomide.com]
Sent: Saturday, June 08, 2013 12:57 PM
To: R, Sricharan
Cc: Shilimkar, Santosh; Paul Walmsley; linux-omap@vger.kernel.org;
linux-arm-ker...@lists.infradead.org; Nayak, Rajendra; Cousson, Benoit; Kristo,
Tero; K, Ambresh
Subject: Re: [PATCH V2 14/14] ARM: OMAP4: hwmod data: Clean up the data
Sorry for top posting. Can you just add static inlines functions in header file
and #ifdef it for OMAP5.
Regards,
Santosh
From: Stehle, Vincent
Sent: Thursday, May 16, 2013 7:59 PM
To: Shilimkar, Santosh
Cc: Vincent Stehlé; Tony Lindgren; linux-omap
Sorry for top posting ...
I will pick the ack and update commit log to prepare new pull request
for you.
Regards,
Santosh
From: Tony Lindgren [t...@atomide.com]
Sent: Thursday, March 28, 2013 1:28 AM
To: Shilimkar, Santosh
Cc: linux-omap@vger.kernel.org
On Wed, Oct 3, 2012 at 5:05 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Hi Santosh, Tero,
I just added my 4460/PandaES to my board farm for automated PM testing
and see that basic suspend/resume tests don't work in mainline. It
fails on v3.6 and linux-next,arm-soc/for-next.
Adding
On Sun, Sep 30, 2012 at 1:09 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Sep 28, 2012 at 07:10:08PM +0530, Lokesh Vutla wrote:
omap_reserve() is a stub for omap1. So creating a
stub locally in mach-omap1. And moving the definition
to mach-omap2.
This helps in
On Wed, Sep 12, 2012 at 12:44 PM, R Sricharan r.sricha...@ti.com wrote:
memblock_steal tries to reserve physical memory during boot.
When the requested size is not aligned on the section size
then, the remaining memory available for lowmem becomes
unaligned on the section boundary. There is a
+ Peter, Liam in case they haven't seen the issue yet.
On Fri, Sep 28, 2012 at 12:28 PM, Vutla, Lokesh lokeshvu...@ti.com wrote:
Hi,
I see a module build failure in linux-next tree.
Any one else facing this issue or I am missing something.
Using master branch on
On Fri, Sep 28, 2012 at 8:25 PM, Tony Lindgren t...@atomide.com wrote:
* Lokesh Vutla lokeshvu...@ti.com [120928 06:41]:
Move plat/dma.h header to platform_data/dma-omap.h as
part of the single zImage work.
Hmm there's no platform data in this header, just
exported things for drivers to
On Fri, Sep 28, 2012 at 8:35 PM, Tony Lindgren t...@atomide.com wrote:
* Shilimkar, Santosh santosh.shilim...@ti.com [120928 08:02]:
On Fri, Sep 28, 2012 at 8:25 PM, Tony Lindgren t...@atomide.com wrote:
* Lokesh Vutla lokeshvu...@ti.com [120928 06:41]:
Move plat/dma.h header
On Fri, Sep 28, 2012 at 1:56 AM, Tony Lindgren t...@atomide.com wrote:
Please see below a status update on the remaining problem
plat headers.
Note that all patches should be against current linux next
in this case.
* Tony Lindgren t...@atomide.com [120920 16:30]:
$ ls
On Sun, Sep 23, 2012 at 3:29 AM, Paul E. McKenney
paul...@linux.vnet.ibm.com wrote:
On Sat, Sep 22, 2012 at 01:10:43PM -0700, Paul E. McKenney wrote:
On Sat, Sep 22, 2012 at 06:42:08PM +, Paul Walmsley wrote:
On Fri, 21 Sep 2012, Paul E. McKenney wrote:
[...]
And here is a patch. I am
On Sun, Sep 23, 2012 at 12:01 AM, Paul Walmsley p...@pwsan.com wrote:
cc Santosh
Hi Igor,
I regret the delay in responding,
On Fri, 7 Sep 2012, Igor Grinberg wrote:
On 09/05/12 18:44, Paul Walmsley wrote:
* CM-T3517: L3 in-band error with USB OTG during boot
- Cause unknown;
On Sat, Sep 22, 2012 at 10:41 PM, Chris Hoffmann chrmhoffm...@gmail.com wrote:
On 09/22/2012 07:45 AM, Shilimkar, Santosh wrote:
On Sat, Sep 22, 2012 at 4:19 AM, Chris Hoffmann chrmhoffm...@gmail.com
wrote:
Hi,
We're trying to get a custom 4430 board (aka. nook tablet with OMAP4430
ES2.3
Paul,
On Sat, Sep 22, 2012 at 1:41 PM, Paul Walmsley p...@pwsan.com wrote:
Fix a memory corruption bug caused by commit
247c445c0fbd52c77e497ff5bfcf0dceb8afea8d (ARM: OMAP5: Add the
WakeupGen IP updates) and commit
ec2c0825ca3183a646a24717966cc7752e8b0393 (ARM: OMAP2+: Remove
hardcoded
On Sat, Sep 22, 2012 at 2:16 AM, Tony Lindgren t...@atomide.com wrote:
* Shilimkar, Santosh santosh.shilim...@ti.com [120919 00:54]:
(With fixed git URL)
On Wed, Sep 19, 2012 at 1:21 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Tony,
Here is the pull request which
On Sat, Sep 22, 2012 at 4:19 AM, Chris Hoffmann chrmhoffm...@gmail.com wrote:
Hi,
We're trying to get a custom 4430 board (aka. nook tablet with OMAP4430
ES2.3 HS TWL6030 ES2.1) working with p-android-omap-3.0 on android jelly
bean. The board works quite well, but we experience random hangs
Paul,
On Thu, Sep 20, 2012 at 10:47 PM, Paul Walmsley p...@pwsan.com wrote:
Hi Jon, Will, Ming, et al.,
Have queued most of these for 3.7 with the exception of the OMAP4430
CTI-related patches (which look to me like 3.8 material) and the PM
runtime suspend/resume patch (which looks to me
On Thu, Sep 20, 2012 at 11:13 PM, Paul Walmsley p...@pwsan.com wrote:
Hi
On Thu, 20 Sep 2012, Shilimkar, Santosh wrote:
On Thu, Sep 20, 2012 at 10:47 PM, Paul Walmsley p...@pwsan.com wrote:
Have queued most of these for 3.7 with the exception of the OMAP4430
CTI-related patches (which
(With fixed git URL)
On Wed, Sep 19, 2012 at 1:21 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Tony,
Here is the pull request which enables the architected cpu local timer
support for OMAP5 devices.
The following changes since commit
5698bd757d55b1bb87edd1a9744ab09c142abfc2:
On Tue, Sep 18, 2012 at 11:23 PM, Tony Lindgren t...@atomide.com wrote:
* Shilimkar, Santosh santosh.shilim...@ti.com [120917 23:07]:
On Tue, Sep 18, 2012 at 3:09 AM, Tony Lindgren t...@atomide.com wrote:
* Tony Lindgren t...@atomide.com [120917 14:39]:
* Benoit Cousson b-cous...@ti.com
On Wed, Sep 19, 2012 at 8:28 PM, Arnd Bergmann a...@arndb.de wrote:
On Monday 17 September 2012, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [120914 02:21]:
OMAP interconnect drivers are used for the interconnect error handling.
Since they are bus driver, lets move it
On Thu, Sep 20, 2012 at 12:27 AM, Arnd Bergmann a...@arndb.de wrote:
On Monday 17 September 2012, Tony Lindgren wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [120914 02:21]:
OMAP interconnect drivers are used for the interconnect error handling.
Since they are bus driver, lets move it
On Tue, Sep 18, 2012 at 3:09 AM, Tony Lindgren t...@atomide.com wrote:
* Tony Lindgren t...@atomide.com [120917 14:39]:
* Benoit Cousson b-cous...@ti.com [120913 01:57]:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real
On Tue, Sep 18, 2012 at 2:08 AM, Tony Lindgren t...@atomide.com wrote:
* Sebastian Reichel s...@debian.org [120913 14:58]:
Hi,
Are there plans to add crypto acceleration support to OMAP4? Has
this hardware component been removed from OMAP4? I tried to load the
code written for OMAP3 on
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com
On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson b-cous...@ti.com wrote:
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 09/11/2012 11:29 AM, Shilimkar, Santosh wrote:
Benoit,
On Mon, Sep 10, 2012 at 7
On Thu, Sep 13, 2012 at 3:30 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, Sep 13, 2012 at 2:57 PM, Benoit Cousson b-cous...@ti.com wrote:
On 09/13/2012 11:00 AM, Shilimkar, Santosh wrote:
On Thu, Sep 13, 2012 at 2:26 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh
On Thu, Sep 13, 2012 at 6:23 PM, Dave Martin dave.mar...@linaro.org wrote:
On Thu, Sep 13, 2012 at 11:20:49AM +0100, Lorenzo Pieralisi wrote:
In processors like A15/A7 L2 cache is unified and integrated within the
processor cache hierarchy, so that it is not considered an outer cache
anymore.
On Thu, Sep 13, 2012 at 6:38 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Thu, Sep 13, 2012 at 06:31:35PM +0530, Shilimkar, Santosh wrote:
In the series, there is patch [PATCH 3/6] which adds an
API which let you operate on a specific level.
Which is introduced but as far
On Wed, Sep 12, 2012 at 6:02 AM, Paul Walmsley p...@pwsan.com wrote:
Remove some unnecessary plat/ includes that are interfering with multi-subarch
ARM kernels.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc: Kevin Hilman khil...@ti.com
Cc: Rafael J. Wysocki r...@sisk.pl
Acked-by: Kevin
On Wed, Sep 12, 2012 at 6:16 PM, Cyril Chemparathy cy...@ti.com wrote:
On 9/12/2012 1:50 AM, R Sricharan wrote:
Even if CONFIG_DMA_ADDR_64BIT_T is enabled by the defconfig,
the feature is not getting selected.
Adding a string description in the Kconfig resolves this.
But not sure if this
On Wed, Sep 12, 2012 at 7:27 PM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Wed, Sep 12, 2012 at 6:02 AM, Paul Walmsley p...@pwsan.com wrote:
Remove some unnecessary plat/ includes that are interfering with
multi-subarch
ARM
On Tue, Sep 11, 2012 at 12:25 AM, Tony Lindgren t...@atomide.com wrote:
* Shilimkar, Santosh santosh.shilim...@ti.com [120908 01:20]:
Will you able to pick up these couple of wakeupgen fixes from here or
do you want me to send you a pull request for 3.6-rc5/6
I can pick them into fixes
On Tue, Sep 11, 2012 at 12:07 PM, Paul Walmsley p...@pwsan.com wrote:
On Tue, 11 Sep 2012, Shilimkar, Santosh wrote:
On Tue, Sep 11, 2012 at 12:25 AM, Tony Lindgren t...@atomide.com wrote:
* Shilimkar, Santosh santosh.shilim...@ti.com [120908 01:20]:
Will you able to pick up these couple
Jon,
On Mon, Sep 10, 2012 at 8:53 PM, Jon Hunter jon-hun...@ti.com wrote:
This series adds PMU support for OMAP4 devices. This is based upon Will
Deacons
series [1] and re-based upon the latest arm-soc next/cleanup branch (3.6-rc3)
that includes Will's series. It has been re-based upon this
On Tue, Sep 11, 2012 at 12:13 PM, Paul Walmsley p...@pwsan.com wrote:
On Tue, 11 Sep 2012, Shilimkar, Santosh wrote:
On Tue, Sep 11, 2012 at 12:07 PM, Paul Walmsley p...@pwsan.com wrote:
On Tue, 11 Sep 2012, Shilimkar, Santosh wrote:
On Tue, Sep 11, 2012 at 12:25 AM, Tony Lindgren t
Benoit,
On Mon, Sep 10, 2012 at 7:09 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com wrote:
[...]
Silly question: Don't we have one arch-timer per CPU?
It is per CPU just like A9 TWD
Shouldn't we have two nodes
Arnd,
On Tue, Sep 11, 2012 at 6:32 PM, Arnd Bergmann a...@arndb.de wrote:
Platform data for device drivers should be defined in
include/linux/platform_data/*.h, not in the architecture
and platform specific directories.
This moves such data out of the omap include directories
On Tue, Sep 11, 2012 at 7:47 PM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 11 September 2012, Shilimkar, Santosh wrote:
Just curious to know how you came with some of the above header names ?
plat/mcbsp --- dsp-mcbsp.h
There is no connection of DSP with McBSP. omap-mcbsp.h would been
On Wed, Sep 12, 2012 at 11:21 AM, R Sricharan r.sricha...@ti.com wrote:
memblock_steal tries to reserve physical memory during boot.
When the requested size is not aligned on the section size
then, the remaining memory available for lowmem becomes
unaligned on the section boundary. There is a
Thomas,
On Mon, Sep 10, 2012 at 3:58 PM, Thomas Gleixner t...@linutronix.de wrote:
On Mon, 10 Sep 2012, NeilBrown wrote:
The IRQCHIP_MASK_ON_SUSPEND flag seems to be hard to use correctly, so either
I'm understanding it wrongly, or it could be made easier to use.
If the first case, I'm
Benoit,
On Mon, Aug 13, 2012 at 4:37 PM, Santosh Shilimkar
santosh.shilim...@ti.com wrote:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by: Santosh Shilimkar santosh.shilim...@ti.com
---
On Mon, Sep 10, 2012 at 6:17 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
Enable Cortex A15 generic timer support for OMAP5 based SOCs.
The CPU local timers run on the free running real time counter clock.
Signed-off-by:
On Mon, Sep 10, 2012 at 6:44 PM, Benoit Cousson b-cous...@ti.com wrote:
On 09/10/2012 03:01 PM, Shilimkar, Santosh wrote:
On Mon, Sep 10, 2012 at 6:17 PM, Benoit Cousson b-cous...@ti.com
wrote:
Hi Santosh,
On 08/13/2012 01:07 PM, Santosh Shilimkar wrote:
Enable Cortex A15 generic
On Sat, Sep 8, 2012 at 3:07 AM, Kevin Hilman
khil...@deeprootsystems.com wrote:
Hi Neil,
NeilBrown ne...@suse.de writes:
On Thu, 6 Sep 2012 11:18:09 +0530 Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, Sep 6, 2012 at 8:35 AM, NeilBrown ne...@suse.de wrote:
On Mon, 3 Sep 2012
Tony,
On Thu, Sep 6, 2012 at 12:05 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, Sep 6, 2012 at 5:04 AM, Paul Walmsley p...@pwsan.com wrote:
The wakeupgen context-save code reads and stores the AUXCOREBOOT0 and
AUXCOREBOOT1 register contents twice. This seems like
On Thu, Sep 6, 2012 at 5:04 AM, Paul Walmsley p...@pwsan.com wrote:
The wakeupgen context-save code reads and stores the AUXCOREBOOT0 and
AUXCOREBOOT1 register contents twice. This seems like a waste of
time, so, remove the duplicates.
Signed-off-by: Paul Walmsley p...@pwsan.com
Cc:
On Thu, Sep 6, 2012 at 12:32 PM, NeilBrown ne...@suse.de wrote:
On Thu, 6 Sep 2012 11:18:09 +0530 Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, Sep 6, 2012 at 8:35 AM, NeilBrown ne...@suse.de wrote:
On Mon, 3 Sep 2012 22:59:06 -0700 Shilimkar, Santosh
santosh.shilim...@ti.com
On Thu, Sep 6, 2012 at 1:21 PM, NeilBrown ne...@suse.de wrote:
On Thu, 6 Sep 2012 12:57:46 +0530 Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Thu, Sep 6, 2012 at 12:32 PM, NeilBrown ne...@suse.de wrote:
On Thu, 6 Sep 2012 11:18:09 +0530 Shilimkar, Santosh
santosh.shilim...@ti.com
On Wed, Sep 5, 2012 at 5:11 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Tony,
On 09/05/2012 02:03 AM, Tony Lindgren wrote:
If NR_IRQS is less than MAX_IRQS, we end up writing past the
irq_target_cpu array in omap_wakeupgen_init():
/* Associate all the IRQs to boot CPU like GIC init
On Thu, Sep 6, 2012 at 8:35 AM, NeilBrown ne...@suse.de wrote:
On Mon, 3 Sep 2012 22:59:06 -0700 Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Sun, Aug 26, 2012 at 6:29 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Sun, Aug 26, 2012 at 3:53 PM, NeilBrown ne...@suse.de
On Wed, Sep 5, 2012 at 5:33 AM, Tony Lindgren t...@atomide.com wrote:
If NR_IRQS is less than MAX_IRQS, we end up writing past the
irq_target_cpu array in omap_wakeupgen_init():
/* Associate all the IRQs to boot CPU like GIC init does. */
for (i = 0; i max_irqs; i++)
On Mon, Sep 3, 2012 at 8:04 AM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
Sorry for the delay, I missed that email :-(
On 08/23/2012 09:32 AM, Santosh Shilimkar wrote:
Benoit,
On Monday 13 August 2012 04:30 PM, Santosh Shilimkar wrote:
These are the few device tree related
On Mon, Sep 3, 2012 at 9:20 AM, Benoit Cousson b-cous...@ti.com wrote:
Remove a useless comment and move GIC controller outside
of the OCP node since it does use the MPU internal bus and
not the OCP.
This will not change the functionality but will reflect the
reality more accurately.
On Sun, Aug 26, 2012 at 6:29 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Sun, Aug 26, 2012 at 3:53 PM, NeilBrown ne...@suse.de wrote:
On Sun, 26 Aug 2012 09:47:50 +0530 Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
+ Jon,
On Sat, Aug 25, 2012 at 5:14 PM, NeilBrown ne
On Wed, Aug 29, 2012 at 8:24 AM, Aaro Koskinen aaro.koski...@iki.fi wrote:
OMAP4-specific code should be executed only if we are running on
OMAP4. Otherwise it may break multi-OMAP kernels. Found by reading
the code.
Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi
---
Looks good.
On Wed, Aug 29, 2012 at 8:24 AM, Aaro Koskinen aaro.koski...@iki.fi wrote:
In some OMAP3 HS devices (at least Nokia N9 and N950), the public SRAM
seems to conflict with secure portition of SRAM. When booting the 3.6-rc3
kernel (and also earlier) on these devices, the kernel gets tainted with
On Tue, Aug 28, 2012 at 5:20 AM, Aaro Koskinen aaro.koski...@iki.fi wrote:
Hi,
On Mon, Aug 27, 2012 at 05:17:30PM -0700, Shilimkar, Santosh wrote:
On Mon, Aug 27, 2012 at 4:26 PM, Aaro Koskinen aaro.koski...@iki.fi wrote:
I tried bypassing the whole SRAM init, but the device does not seem
On Tue, Aug 28, 2012 at 4:09 PM, Aaro Koskinen aaro.koski...@iki.fi wrote:
Hi,
On Tue, Aug 28, 2012 at 07:19:38AM -0700, Shilimkar, Santosh wrote:
Or the PPA has resized the secure area of 16K. As you have seen the issue
on one OMAP3 device, it makes sense to takeout that 16K from the public
On Mon, Aug 27, 2012 at 2:03 PM, Aaro Koskinen aaro.koski...@iki.fi wrote:
When booting kernel on RM-680/N950, the console is flooded with:
[6.894348] In-band Error seen by MPU at address 0
[6.894348] [ cut here ]
[6.894378] WARNING: at
On Mon, Aug 27, 2012 at 3:02 PM, Aaro Koskinen aaro.koski...@iki.fi wrote:
Hi,
On Mon, Aug 27, 2012 at 02:35:57PM -0700, Shilimkar, Santosh wrote:
- pr_err(%s seen by %s %s at address %x\n,
+ pr_err_ratelimited(%s seen by %s %s at address %x\n
On Mon, Aug 27, 2012 at 3:26 PM, Igor Grinberg grinb...@compulab.co.il wrote:
Currently, omap2_sync32k_clocksource_init() function initializes the 32K
timer as the system clock source regardless of the CONFIG_OMAP_32K_TIMER
setting.
Fix this by providing a default implementation for
On Mon, Aug 27, 2012 at 4:26 PM, Aaro Koskinen aaro.koski...@iki.fi wrote:
On Mon, Aug 27, 2012 at 03:12:07PM -0700, Shilimkar, Santosh wrote:
On Mon, Aug 27, 2012 at 3:02 PM, Aaro Koskinen aaro.koski...@iki.fi wrote:
Hi,
On Mon, Aug 27, 2012 at 02:35:57PM -0700, Shilimkar, Santosh wrote
On Sun, Aug 26, 2012 at 3:53 PM, NeilBrown ne...@suse.de wrote:
On Sun, 26 Aug 2012 09:47:50 +0530 Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
+ Jon,
On Sat, Aug 25, 2012 at 5:14 PM, NeilBrown ne...@suse.de wrote:
Current kernel will wake from suspend on an event
+ Jon,
On Sat, Aug 25, 2012 at 5:14 PM, NeilBrown ne...@suse.de wrote:
Current kernel will wake from suspend on an event on any active
GPIO even if enable_irq_wake() wasn't called.
There are two reasons that the hardware wake-enable bit should be set:
1/ while non-suspended the CPU might
On Fri, Aug 24, 2012 at 2:30 AM, Peter Meerwald pme...@pmeerw.net wrote:
On Wed, 18 Jul 2012, Javier Martinez Canillas wrote:
On Wed, Jul 18, 2012 at 10:36 AM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Wed, Jul 18, 2012 at 1:14 PM, S, Venkatraman svenk...@ti.com
wrote
On Fri, Aug 24, 2012 at 3:12 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Aug 24, 2012 at 09:51:15AM +0200, Peter Meerwald wrote:
the commit just sets CONFIG_DMA_OMAP=y and CONFIG_DMADEVICES=y in
omap2plus_defconfig; this does not help people updating the kernel while
On Fri, Aug 24, 2012 at 4:09 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Aug 24, 2012 at 03:51:26PM +0530, Shilimkar, Santosh wrote:
On Fri, Aug 24, 2012 at 3:12 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Fri, Aug 24, 2012 at 09:51:15AM +0200, Peter
On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
This provides PL310 Level 2 Cache Controller Device Tree
support for OMAP4
On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi ba...@ti.com wrote:
The current support is known to be broken and
a later patch will come re-adding it using
dma engine API.
Signed-off-by: Felipe Balbi ba...@ti.com
---
Thanks Felipe !!
One less driver now towards OMAP DMA
engine conversion.
On Tue, Aug 21, 2012 at 3:54 PM, Felipe Balbi ba...@ti.com wrote:
On Tue, Aug 21, 2012 at 03:11:51PM +0530, Shilimkar, Santosh wrote:
On Mon, Aug 20, 2012 at 9:21 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson b-cous...@ti.com wrote
On Tue, Aug 21, 2012 at 3:50 PM, Felipe Balbi ba...@ti.com wrote:
On Tue, Aug 21, 2012 at 03:14:19PM +0530, Shilimkar, Santosh wrote:
On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi ba...@ti.com wrote:
The current support is known to be broken and
a later patch will come re-adding it using
On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi ba...@ti.com wrote:
Everytime we're done using our TTY, we want
the pm timer to be reinitilized. By sticking
to pm_runtime_pm_autosuspend() we make sure
that this will always be the case.
Signed-off-by: Felipe Balbi ba...@ti.com
---
On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi ba...@ti.com wrote:
Hi guys,
here's a series of cleanup patches to the OMAP serial
driver. A later series could be made re-implementing
DMA using the DMA Engine API. Note that for RX DMA
we could be using RX Timeout IRQ as a hint that we better
On Tue, Aug 21, 2012 at 4:14 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
[...]
From 91d6cb4f999061c8cfc844a3916ee3384f2e488a Mon Sep 17 00:00:00 2001
From: Santosh Shilimkar santosh.shilim...@ti.com
Date: Wed, 4 Jul 2012 17:57:34 +0530
Subject: [PATCH 1/2 v2] ARM: OMAP4: Add L2
On Tue, Aug 21, 2012 at 4:27 PM, Felipe Balbi ba...@ti.com wrote:
On Tue, Aug 21, 2012 at 04:12:11PM +0530, Shilimkar, Santosh wrote:
On Tue, Aug 21, 2012 at 2:45 PM, Felipe Balbi ba...@ti.com wrote:
Everytime we're done using our TTY, we want
the pm timer to be reinitilized. By sticking
On Mon, Aug 20, 2012 at 12:08 PM, S, Venkatraman svenk...@ti.com wrote:
On Fri, Aug 17, 2012 at 11:43 PM, Puttagunta, Viswanath vi...@ti.com
wrote:
On Fri, Aug 17, 2012 at 12:28 PM, S, Venkatraman svenk...@ti.com
wrote:
On Fri, Aug 17, 2012 at 9:35 PM, Semen Protsenko
Tomi,
On Mon, Aug 20, 2012 at 1:38 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
Hi,
Anyone ideas what could I do to debug this further? The problem exists
on v3.6-rc2.
Can you try merging [1] {[GIT PULL] arm-soc: bug fixes for v3.6-rc3}
and see if it helps.
Regards
Santosh
[1]
On Mon, Aug 20, 2012 at 2:24 PM, Tomi Valkeinen tomi.valkei...@ti.com wrote:
Hi,
On Mon, 2012-08-20 at 13:58 +0530, Shilimkar, Santosh wrote:
Tomi,
On Mon, Aug 20, 2012 at 1:38 PM, Tomi Valkeinen tomi.valkei...@ti.com
wrote:
Hi,
Anyone ideas what could I do to debug this further
On Mon, Aug 20, 2012 at 7:21 PM, Benoit Cousson b-cous...@ti.com wrote:
Hi Santosh,
On 08/13/2012 01:00 PM, Santosh Shilimkar wrote:
This provides PL310 Level 2 Cache Controller Device Tree
support for OMAP4 based devices.
Cc: Benoit Cousson b-cous...@ti.com
Signed-off-by: Santosh
On Tue, Aug 14, 2012 at 11:52 AM, Hiremath, Vaibhav hvaib...@ti.com wrote:
On Tue, Aug 14, 2012 at 11:46:35, Shilimkar, Santosh wrote:
On Mon, Aug 13, 2012 at 11:05 PM, Vaibhav Hiremath hvaib...@ti.com
wrote:
[...]
Also, does it make sense to get rid of hardcoded values above
On Fri, Aug 17, 2012 at 12:15 AM, Greg KH gre...@linuxfoundation.org wrote:
On Mon, Aug 13, 2012 at 10:57:06AM +0530, Shilimkar, Santosh wrote:
Greg,
On Wed, Jul 18, 2012 at 12:14 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Tue, Jul 17, 2012 at 11:28 PM, Greg KH gre
Jean,
On Wed, Aug 15, 2012 at 3:32 PM, Jean Pihet jean.pi...@newoldbits.com wrote:
Here is a re-spin after some comments and suggestions after review.
Implement the functional states for the power domains:
- unify the API to use the functional states. pwrdm_set_next_fpwrst
now is the
Paul,
On Thu, Aug 16, 2012 at 6:18 AM, Paul Walmsley p...@pwsan.com wrote:
Hi Santosh,
On Wed, 15 Aug 2012, Shilimkar, Santosh wrote:
On Wed, Aug 15, 2012 at 3:32 PM, Jean Pihet jean.pi...@newoldbits.com
wrote:
I didn't find any mention here about why are we going in this path
On Mon, Aug 13, 2012 at 11:05 PM, Vaibhav Hiremath hvaib...@ti.com wrote:
On 8/13/2012 4:37 PM, Santosh Shilimkar wrote:
The real time counter also called master counter, is a free-running
counter. It produces the count used by the CPU local timer peripherals
in the MPU cluster. The
Sourav,
On Mon, Aug 13, 2012 at 3:35 PM, Sourav Poddar sourav.pod...@ti.com wrote:
The following patch series add i2c support for omap5.
As well as enable I2C based devices like pressure and temperature
through device tree. Also add onchip keypad dts data.
Cc: Benoit Cousson
On Sun, Aug 12, 2012 at 4:27 PM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
Found this with the cubox, which wants to obtain large blocks of
RAM for the GPU and VPU devices at boot time. I don't believe
any other platforms care where the memory comes from, so I think
this is safe.
Greg,
On Wed, Jul 18, 2012 at 12:14 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Tue, Jul 17, 2012 at 11:28 PM, Greg KH gre...@linuxfoundation.org wrote:
On Tue, Jul 17, 2012 at 10:37:45PM +0530, Shilimkar, Santosh wrote:
On Tue, Jul 17, 2012 at 10:06 PM, Greg KH gre
On Fri, Aug 10, 2012 at 11:38 AM, DebBarma, Tarun Kanti
tarun.ka...@ti.com wrote:
On Thu, Aug 9, 2012 at 8:28 PM, Kevin Hilman khil...@ti.com wrote:
DebBarma, Tarun Kanti tarun.ka...@ti.com writes:
On Wed, Aug 8, 2012 at 10:40 PM, Kevin Hilman khil...@ti.com wrote:
Tarun Kanti DebBarma
On Thu, Aug 9, 2012 at 12:38 PM, Rajendra Nayak rna...@ti.com wrote:
The 4430 OPP table was being registered for all other OMAP4 variants
too, like 4460 and 4470 causing issues with cpufreq driver
enabled. 4460 and 4470 devices have different OPPs as compared to
4430, and they should be
On Wed, Aug 8, 2012 at 4:24 PM, Rajendra Nayak rna...@ti.com wrote:
On OMAP4, if the first CPU fails to get a valid frequency table (this
could happen if the platform does not register any OPP table), the
subsequent CPU instances end up dealing with a NULL freq_table and
crash. Add a check
On Wed, Aug 8, 2012 at 7:28 PM, Tarun Kanti DebBarma tarun.ka...@ti.com wrote:
Add *remove* callback so that necessary cleanup operations are
performed when device is unregistered. The device is deleted
from the list and associated clock handle is released by
calling clk_put() and irq
On Wed, Aug 8, 2012 at 10:58 PM, Kevin Hilman khil...@ti.com wrote:
Shilimkar, Santosh santosh.shilim...@ti.com writes:
On Wed, Aug 8, 2012 at 4:24 PM, Rajendra Nayak rna...@ti.com wrote:
On OMAP4, if the first CPU fails to get a valid frequency table (this
could happen if the platform
On Wed, Aug 8, 2012 at 10:45 PM, Kevin Hilman khil...@ti.com wrote:
Santosh Shilimkar santosh.shilim...@ti.com writes:
OMAP4 sleep entry code even though itself don't use many CPU registers
makes call to the v7_flush_dcache_all() which uses them. Since
v7_flush_dcache_all() doesn't make use
On Tue, Aug 7, 2012 at 12:30 PM, Tony Lindgren t...@atomide.com wrote:
* Shilimkar, Santosh santosh.shilim...@ti.com [120726 00:27]:
On Tue, Jul 10, 2012 at 10:33 AM, Tony Lindgren t...@atomide.com wrote:
* Santosh Shilimkar santosh.shilim...@ti.com [120709 08:07]:
Tony,
Please pull
On Tue, Jul 31, 2012 at 6:26 PM, Poddar, Sourav sourav.pod...@ti.com wrote:
Hi Santosh,
On Tue, Jul 31, 2012 at 6:02 PM, Shilimkar, Santosh
santosh.shilim...@ti.com wrote:
On Tue, Jul 31, 2012 at 8:52 AM, Felipe Balbi ba...@ti.com wrote:
Hi,
On Tue, Jul 31, 2012 at 10:23:16AM +0530
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