Re: [PATCH net-next 05/22] cxgb4: Add T5 write combining support

2013-03-13 Thread Casey Leedom
On 03/13/13 08:43, David Laight wrote: From my recollection of the x86 architecture, the memory barriers are hardly ever needed, certainly not in the places where, for example a ppc needs them. I'd actually suspect that the normal wmb() for x86 should be a nop. About the only place where any o

RE: [PATCH net-next 05/22] cxgb4: Add T5 write combining support

2013-03-13 Thread David Laight
> >>> + writel(n, adap->bar2 + q->udb + 8); > >>> +#if defined(CONFIG_X86_32) || defined(CONFIG_X86_64) > >>> + asm volatile("sfence" : : : "memory"); > >>> +#endif > >> There is absolutely no way I'm letting anyone put crap like this > >> into a driver. > >

Re: [PATCH net-next 05/22] cxgb4: Add T5 write combining support

2013-03-13 Thread Vipul Pandya
On 12-03-2013 20:12, Steve Wise wrote: > On 3/12/2013 7:19 AM, David Miller wrote: >> From: Vipul Pandya >> Date: Tue, 12 Mar 2013 17:16:17 +0530 >> >>> + writel(n, adap->bar2 + q->udb + 8); >>> +#if defined(CONFIG_X86_32) || defined(CONFIG_X86_64) >>> +

Re: [PATCH net-next 05/22] cxgb4: Add T5 write combining support

2013-03-12 Thread Steve Wise
On 3/12/2013 7:19 AM, David Miller wrote: From: Vipul Pandya Date: Tue, 12 Mar 2013 17:16:17 +0530 + writel(n, adap->bar2 + q->udb + 8); +#if defined(CONFIG_X86_32) || defined(CONFIG_X86_64) + asm volatile("sfence" : : : "memory"); +#endif

Re: [PATCH net-next 05/22] cxgb4: Add T5 write combining support

2013-03-12 Thread David Miller
From: Vipul Pandya Date: Tue, 12 Mar 2013 17:16:17 +0530 > + writel(n, adap->bar2 + q->udb + 8); > +#if defined(CONFIG_X86_32) || defined(CONFIG_X86_64) > + asm volatile("sfence" : : : "memory"); > +#endif There is absolutely no way I'm letting an