Cc Marz Zyngier
Cc Dirk Behme
Cc devicetree
Cc linux-renesas-soc
Drop linux-sh
On Wed, Dec 9, 2015 at 9:23 AM, Geert Uytterhoeven wrote:
> On Tue, Nov 3, 2015 at 3:28 PM, Mark Rutland wrote:
>> On Wed, Oct 21, 2015 at 03:34:39PM +0200, Geert Uytterhoeven wrote:
>>> On Thu, Oct 15, 2015 at 12:58
On Tue, Feb 2, 2016 at 2:31 PM, Simon Horman wrote:
> Use GIC_* defines for GIC interrupt cells in r8a7795 device tree.
>
> Signed-off-by: Simon Horman
Acked-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
On 15/02/16 08:16, Geert Uytterhoeven wrote:
> Cc Marz Zyngier
> Cc Dirk Behme
> Cc devicetree
> Cc linux-renesas-soc
> Drop linux-sh
>
> On Wed, Dec 9, 2015 at 9:23 AM, Geert Uytterhoeven
> wrote:
>> On Tue, Nov 3, 2015 at 3:28 PM, Mark Rutland wrote:
>>> On Wed, Oct 21, 2015 at 03:34:39PM +02
On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart
wrote:
> The parent clock isn't documented in the datasheet, use S2D1 as a best
> guess for now.
Looks like a good guess...
I assume the driver doesn't depend on the clock rate?
> Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart
wrote:
> The parent clock hasn't been validated yet.
I assume the driver doesn't depend on the clock rate?
> Signed-off-by: Laurent Pinchart
Reviewed-by: Geert Uytterhoeven
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoe
On 02/14/2016 05:55 PM, Niklas Söderlund wrote:
> A V4L2 driver for Renesas R-Car VIN IP cores that do not depend on
> soc_camera. The driver is heavily based on its predecessor and aims to
> replace the soc_camera driver.
Fantastic! I've been hoping that this would be done at some point. It
was v
Hi Laurent,
On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart
wrote:
> The FCP is a companion module of video processing modules in the
> Renesas R-Car Gen3 SoCs. It provides data compression and decompression,
> data caching, and converting of AXI transaction in order to reduce the
"conversion"
Hi Laurent,
On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart
wrote:
> The FCPs handle the interface between various IP cores and memory. Add
> the instances related to the VSP2s.
>
> Signed-off-by: Laurent Pinchart
> ---
> arch/arm64/boot/dts/renesas/r8a7795.dtsi | 63
> ++
Hi Laurent,
On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart
wrote:
> The r8a7795 has 9 VSP instances with various capabilities.
>
> Only the VSPD instances are currently enabled as the other 5 instances
> cause the following crash when reading the version register.
>
> [5.284206] Bad mode i
Hi Marc,
On Mon, Feb 15, 2016 at 9:45 AM, Marc Zyngier wrote:
> On 15/02/16 08:16, Geert Uytterhoeven wrote:
>> On Wed, Dec 9, 2015 at 9:23 AM, Geert Uytterhoeven
>> wrote:
>>> On Tue, Nov 3, 2015 at 3:28 PM, Mark Rutland wrote:
On Wed, Oct 21, 2015 at 03:34:39PM +0200, Geert Uytterhoeven
On 02/15/2016 10:28 AM, Hans Verkuil wrote:
>> +static const struct v4l2_ioctl_ops rvin_ioctl_ops = {
>> +.vidioc_querycap= rvin_querycap,
>> +.vidioc_try_fmt_vid_cap = rvin_try_fmt_vid_cap,
>> +.vidioc_g_fmt_vid_cap = rvin_g_fmt_vid_cap,
>> +.vidio
On 15/02/16 10:35, Geert Uytterhoeven wrote:
> Hi Marc,
>
> On Mon, Feb 15, 2016 at 9:45 AM, Marc Zyngier wrote:
>> On 15/02/16 08:16, Geert Uytterhoeven wrote:
>>> On Wed, Dec 9, 2015 at 9:23 AM, Geert Uytterhoeven
>>> wrote:
On Tue, Nov 3, 2015 at 3:28 PM, Mark Rutland wrote:
> On W
On 2/15/2016 4:45 AM, Simon Horman wrote:
Now that Maxim Integrated MAX3355 'extcon' driver and device tree bindings
are upstream along with the 'extcon' hook in the Renesas USBHS driver, we
can add MAX3355 device node to the Porter device tree and properly refer
to it from the USBHS node ins
Hi Sergei,
On Wed, Feb 10, 2016 at 11:37 PM, Sergei Shtylyov
wrote:
>Here's the set of 2 patches against the 'devel' branch of Linus Walleij's
> 'linux-pinctrl.git' repo. Here we add the PFC support for the Renesas R8A7794
> SSI devices and audio clocks.
Thanks!
> [1/2] pinctrl: sh-pfc: r8a
On Sun, Feb 14, 2016 at 5:55 PM, Niklas Söderlund
wrote:
> A V4L2 driver for Renesas R-Car VIN IP cores that do not depend on
> soc_camera. The driver is heavily based on its predecessor and aims to
> replace the soc_camera driver.
Thanks a lot, this will allow me to implement HDMI input properly
From: Magnus Damm
The sh-pfc Pinctrl driver is currently handling SoC-specific
PFC hardware blocks on Arm64, Arm and SH architectures.
For older SoCs using SH cores and some 32-bit Arm SoCs the PFC
hardware also provides GPIO functionality. On the majority of
32-bit Arm SoCs from Renesas and so
From: Magnus Damm
Most pins on the r8a7795 SoC can be configured in GPIO mode for
interrupt and GPIO functionality, while a couple of them can also
be routed to the INTC-EX hardware block (formerly known as IRQC).
On r8a7795 the INTC-EX hardware handles pins IRQ0 -> IRQ5 and
this patch adds supp
Hi Simon, Magnus,
When CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend:
Freezing user space processes ... (elapsed 0.004 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.002 seconds)
done.
PM: suspend of devices complete after 111.948 msecs
CPU boot configuration writes to shmobile_boot_arg, which is located in
the .text section, and thus should not be written to.
As of commit 1d33a354bbb618ba ("ARM: shmobile: Per-CPU SMP boot / sleep
code for SCU SoCs"), and ignoring accidental remainings,
shmobile_boot_arg is always set to MPIDR_HW
If CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend:
Freezing user space processes ... (elapsed 0.004 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.002 seconds)
done.
PM: suspend of devices complete after 111.948 msecs
PM: late suspend of devic
From: Magnus Damm
Add the "intc-ex" clock to the r8a7795 CPG MSSR driver.
The parent clock is assumed to be S3D1 since other INTC
hardware is using this clock.
Signed-off-by: Magnus Damm
---
Developed on top of renesas-drivers-2016-02-09-v4.5-rc3
drivers/clk/shmobile/r8a7795-cpg-mssr.c |
Hi Geert,
On Monday 15 February 2016 10:22:22 Geert Uytterhoeven wrote:
> On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart wrote:
> > The parent clock isn't documented in the datasheet, use S2D1 as a best
> > guess for now.
>
> Looks like a good guess...
> I assume the driver doesn't depend on t
Hi Geert,
On Monday 15 February 2016 10:24:02 Geert Uytterhoeven wrote:
> On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart wrote:
> > The parent clock hasn't been validated yet.
>
> I assume the driver doesn't depend on the clock rate?
Correct.
> > Signed-off-by: Laurent Pinchart
> >
>
> Rev
Hi Geert,
Thank you for the review.
On Monday 15 February 2016 10:32:35 Geert Uytterhoeven wrote:
> On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart wrote:
> > The FCP is a companion module of video processing modules in the
> > Renesas R-Car Gen3 SoCs. It provides data compression and decompres
As of commit 2eaa790989e03900 ("earlycon: Use common framework for
earlycon declarations") it is no longer needer to specify both
EARLYCON_DECLARE() and OF_EARLYCON_DECLARE().
Signed-off-by: Geert Uytterhoeven
---
drivers/tty/serial/sh-sci.c | 5 -
1 file changed, 5 deletions(-)
diff --git
Cfr. commit a9ec81f4ed5c05db ("serial: sh-sci: Drop the interface
clock").
Signed-off-by: Geert Uytterhoeven
---
I plan to queue this up with the other clk-shmobile patches in
clk-shmobile-for-v4.6 and send a pull request later.
Documentation/devicetree/bindings/clock/renesas,cpg-mssr.txt | 2 +
On 15.02.2016 06:46, Kuninori Morimoto wrote:
Hi Dirk
Cc Geert
Besides the distributor and the CPU interface the GIC-400 additionally
supports the virtual interface control blocks and the virtual CPU interfaces.
Add the physical base addresses and size for these.
See
http://infocenter.arm.c
The example in the DT binding documentation uses the preliminary DT
bindings for the r8a7795 MSTP clocks, which never went upstream.
Update the example to use the DT bindings for the upstream Clock Pulse
Generator / Module Standby and Software Reset hardware block.
Signed-off-by: Geert Uytterhoeve
Hi Geert,
Thank you for the review.
On Monday 15 February 2016 10:45:39 Geert Uytterhoeven wrote:
> On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart wrote:
> > The FCPs handle the interface between various IP cores and memory. Add
> > the instances related to the VSP2s.
> >
> > Signed-off-by: L
Hi Geert,
On Monday 15 February 2016 10:58:36 Geert Uytterhoeven wrote:
> On Fri, Feb 12, 2016 at 3:00 AM, Laurent Pinchart wrote:
> > The r8a7795 has 9 VSP instances with various capabilities.
> >
> > Only the VSPD instances are currently enabled as the other 5 instances
> > cause the following
Hi Magnus,
Thank you for the patch.
On Monday 15 February 2016 21:04:38 Magnus Damm wrote:
> From: Magnus Damm
>
> The sh-pfc Pinctrl driver is currently handling SoC-specific
> PFC hardware blocks on Arm64, Arm and SH architectures.
>
> For older SoCs using SH cores and some 32-bit Arm SoCs t
This series provides the necessary preparation to use Lager for testing the
above mentioned features. After this, the rest is done at runtime as described
in the upstream documentation.
This series depends on the i2c-demux-pinctrl driver which is in linux-next
already. Because IIC0/I2C0 is unpopul
From: Wolfram Sang
The Lager board shall be the reference platform for the runtime I2C IP
core switcher and for I2C slave support. Enable the needed drivers for
this.
Signed-off-by: Wolfram Sang
---
arch/arm/configs/shmobile_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch
From: Wolfram Sang
Make it possible to select which I2C IP core you want to run on the
EXIO-A connector. This is the reference how to use this feature. Update
the copyright while we are here.
Signed-off-by: Wolfram Sang
---
arch/arm/boot/dts/r8a7790-lager.dts | 32 +
Hello.
On 2/15/2016 3:36 PM, Geert Uytterhoeven wrote:
As of commit 2eaa790989e03900 ("earlycon: Use common framework for
12-digt ID is enough
earlycon declarations") it is no longer needer to specify both
Needed?
EARLYCON_DECLARE() and OF_EARLYCON_DECLARE().
Signed-off-by: Geert
These are the remaining patches needed to get the SD slots on a Salvator-X
board working. I decided to collect and resend them as a separate series to
make it more clear where we are and to ensure everyone is in the loop :)
There are no changes to patch 1 since it was originally posted. This one s
On Mon, Feb 15, 2016 at 02:34:34PM +0100, Wolfram Sang wrote:
> These are the remaining patches needed to get the SD slots on a Salvator-X
> board working. I decided to collect and resend them as a separate series to
> make it more clear where we are and to ensure everyone is in the loop :)
Sorry,
From: Ai Kyuse
Signed-off-by: Ai Kyuse
Signed-off-by: Yoshihiro Shimoda
[wsa: squashed some fixes and added mmc-caps]
Signed-off-by: Wolfram Sang
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 38
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/
These are the remaining patches needed to get the SD slots on a Salvator-X
board working. I decided to collect and resend them as a separate series to
make it more clear where we are and to ensure everyone is in the loop :)
There are no changes to patch 1 since it was originally posted. This one s
From: Wolfram Sang
Registers are 64bit apart, so we refactor bus_shift handling a little and set
it based on the DT compatible. Also, EXT_ACC is different. It has been tested
on a Salvator-X (Gen3) and, to check for regressions, on a Lager (Gen2).
Signed-off-by: Ai Kyuse
Signed-off-by: Wolfram
From: Ai Kyuse
Add the exposed SD card slots. The on-board eMMC needs to wait until we
fixed the 8bit support (it works with 4bit if you really want it now).
Signed-off-by: Ai Kyuse
Signed-off-by: Wolfram Sang
---
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 83 ++
On Mon, Feb 15, 2016 at 1:55 PM, Laurent Pinchart
wrote:
>> --- 0001/drivers/pinctrl/sh-pfc/Makefile
>> +++ work/drivers/pinctrl/sh-pfc/Makefile 2016-02-15 19:56:50.720513000
> +0900
>> @@ -1,11 +1,8 @@
>> sh-pfc-objs = core.o pinctrl.o
>> -ifeq ($(CONFIG_GPIO_SH_PFC),y)
>>
Hi Wolfram
On Mon, Feb 15, 2016 at 1:57 PM, Wolfram Sang wrote:
> This series provides the necessary preparation to use Lager for testing the
> above mentioned features. After this, the rest is done at runtime as described
> in the upstream documentation.
Thanks for your series!
> This series d
> > I can think of is someone using:
> > a) IIC0 with an external board
> > b) the Lager DTS from upstream unmodified
> > c) a private .config and forgot to activate the i2c-demux-pinctrl
> > driver
> >
> > We could point this person to the working shmobile_defconfig, thou
On Tue, Feb 09, 2016 at 11:57:24PM +0100, Wolfram Sang wrote:
>
> > This is a dependency for adding iommu support to the rcar-dmac driver, cfr.
> > "[PATCH v2 0/5] dmaengine: rcar-dmac: add iommu support for slave
> > transfers".
> > http://www.spinics.net/lists/linux-renesas-soc/msg00066.html
>
> > > This is a dependency for adding iommu support to the rcar-dmac driver,
> > > cfr.
> > > "[PATCH v2 0/5] dmaengine: rcar-dmac: add iommu support for slave
> > > transfers".
> > > http://www.spinics.net/lists/linux-renesas-soc/msg00066.html
> > > https://www.mail-archive.com/linux-renesas-so
On 15.02.2016 11:55, Marc Zyngier wrote:
On 15/02/16 10:35, Geert Uytterhoeven wrote:
Hi Marc,
On Mon, Feb 15, 2016 at 9:45 AM, Marc Zyngier wrote:
On 15/02/16 08:16, Geert Uytterhoeven wrote:
On Wed, Dec 9, 2015 at 9:23 AM, Geert Uytterhoeven wrote:
On Tue, Nov 3, 2015 at 3:28 PM, Mark Ru
On 15/02/16 18:53, Dirk Behme wrote:
> On 15.02.2016 11:55, Marc Zyngier wrote:
>> On 15/02/16 10:35, Geert Uytterhoeven wrote:
>>> Hi Marc,
>>>
>>> On Mon, Feb 15, 2016 at 9:45 AM, Marc Zyngier wrote:
On 15/02/16 08:16, Geert Uytterhoeven wrote:
> On Wed, Dec 9, 2015 at 9:23 AM, Geert Uy
Add a device node for the L2 cache, and link the CPU node to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven
---
v3:
- Drop "arm,data-latency" and "arm,tag-latency" properties, as they
may not be valid when usi
Add the missing "cache-unified" and "cache-level" properties to the
Cortex-A57 cache-controller node.
Signed-off-by: Geert Uytterhoeven
---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
cache-controller nodes", after dropping the "arm,data-latency" and
"arm,tag
Add device nodes for the L2 caches, and link the CPU nodes to them.
The L2 cache for the Cortex-A15 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven
---
v3:
-
Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways), and located in PM domain A3SM.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways), and lo
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven
---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
cache-controller nodes".
---
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A15 CPU cores is 1 MiB large (organized as
64 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven
---
v3:
- Drop "arm,data-latency" and "arm,tag-latency" properties, as they
may not be valid when us
Add a device node for the L2 cache, and link the CPU nodes to it.
The L2 cache for the Cortex-A7 CPU cores is 512 KiB large (organized as
64 KiB x 8 ways).
Signed-off-by: Geert Uytterhoeven
---
v3:
- Change one-line summary prefix to match current arm-soc practices,
v2:
- Drop (incorrect) o
ged one-line summary prefix to match current arm-soc practices.
This series is against renesas-devel-20160215-v4.5-rc4.
It has been tested on r8a73a4/ape6evm, r8a7791/koelsch, r8a7794/alt, and
r8a7795/salvator-x.
For your convenience, I've also pushed this series to
git://git.kernel.org/pub
Print requested power domain state.
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
drivers/soc/renesas/pm-rcar.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/renesas/pm-rcar.c b/drivers/soc/renesas/pm-rcar.c
index bc605d9fbc6ce79c..cc684e9cc8db5d1c 1006
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up ARM CPU cores 1-3 to their respective PM domains.
Note that ARM CPU core 0 cannot be shut off.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Correct sysc "reg" property (#address/s
ARM/arm64: dts: renesas: Add/complete L2
cache-controller nodes"),
- Minor fixes.
This series is against renesas-devel-20160215-v4.5-rc4, with series
"[PATCH v3 0/7] ARM/arm64: dts: renesas: Add/complete L2
cache-controller nodes" applied. It is not yet meant to be applied!
It'
R-Car H3 contains some hardware modules (e.g. VSP and FCP_V) that are
not only located in a power area controlled by the SYSC system
controller, but that are also part of the generic CPG/MSSR clock domain.
Make sure both are handled by enabling module clock PM when the device
for such a hardware mo
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the Cortex-A15 and Cortex-A7 CPU cores and L2 caches/SCUs to
their respective PM domains.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Change one-line summary prefix to match curr
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the first Cortex-A15 CPU core and the Cortex-A15 L2 cache/SCU to
their respective PM domains.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Change one-line summary prefix to match
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the Cortex-A57 CPU cores and the Cortex-A57 and Cortex A53 L2
caches/SCUs to their respective PM domains.
Signed-off-by: Geert Uytterhoeven
---
The SH core was dropped in datasheet
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the Cortex-A15 CPU cores and the Cortex-A15 L2 cache/SCU to
their respective PM domains.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Change one-line summary prefix to match curre
The Renesas R-Car System Controller provides power management for the
CPU cores and various coprocessors, following the generic PM domain
bindings in Documentation/devicetree/bindings/power/power_domain.txt.
This supports R-Car Gen1, Gen2, and Gen3.
Signed-off-by: Geert Uytterhoeven
---
Alternat
Populate the SYSC PM domains from DT.
Special cases, like PM domains containing CPU cores or SCUs, are
handled by scanning the DT topology.
The SYSCIER register value is derived from the PM domains found in DT,
which will allow to get rid of the hardcoded values in pm-rcar-gen2.c.
However, this m
Move the pm-rcar driver to drivers/soc/renesas/, so it can be shared
between arm32 (R-Car H1 and Gen2) and arm64 (R-Car Gen3).
Signed-off-by: Geert Uytterhoeven
---
v2:
- New.
---
arch/arm/mach-shmobile/Kconfig | 8 ++--
arch/arm/mach-shmobile/Makefile
Add a device node for the System Controller, with subnodes that
represent the hardware power area hierarchy.
Hook up the Cortex-A7 CPU cores and the Cortex-A7 L2 cache/SCU to their
respective PM domains.
Signed-off-by: Geert Uytterhoeven
---
v2:
- Change one-line summary prefix to match current
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
check for/support the legacy "gpio-key,wakeup" boolean property to
enable gpio buttons as wakeup source, "wakeup-source" is the new
standard binding.
This patch replaces the legacy "gpio-key,wakeup" with the unified
"wakeup-so
On Mon, Feb 15, 2016 at 04:50:17AM +, Kuninori Morimoto wrote:
>
> Hi
>
> > When finishing the Porter sound support patch, I managed to call the JP3
> > jumper SW3 in the comment. Fix this along with (also miscalled) jumper
> > positions...
> >
> > Fixes: 493b4da7c10c ("ARM: dts: porter: a
On Mon, Feb 15, 2016 at 09:21:29AM +0100, Geert Uytterhoeven wrote:
> On Tue, Feb 2, 2016 at 2:31 PM, Simon Horman
> wrote:
> > Use GIC_* defines for GIC interrupt cells in r8a7795 device tree.
> >
> > Signed-off-by: Simon Horman
>
> Acked-by: Geert Uytterhoeven
Thanks, I have queued this up.
On Mon, Feb 15, 2016 at 01:20:06PM +0100, Geert Uytterhoeven wrote:
> Hi Simon, Magnus,
>
> When CONFIG_DEBUG_RODATA=y, the kernel crashes during system suspend:
>
> Freezing user space processes ... (elapsed 0.004 seconds) done.
> Freezing remaining freezable tasks ... (elapsed 0
Hi Geert,
Thank you for the patch.
On Monday 15 February 2016 22:16:54 Geert Uytterhoeven wrote:
> R-Car H3 contains some hardware modules (e.g. VSP and FCP_V) that are
> not only located in a power area controlled by the SYSC system
> controller, but that are also part of the generic CPG/MSSR cl
Hi Geert,
Thank you for the patch.
On Monday 15 February 2016 22:16:52 Geert Uytterhoeven wrote:
> Print requested power domain state.
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchart
> ---
> v2:
> - New.
> ---
> drivers/soc/renesas/pm-rcar.c | 2 +-
> 1 file changed, 1
On Tue, Feb 9, 2016 at 4:19 PM, Geert Uytterhoeven
wrote:
Quoting in verbatim as we add new recipients.
I don't know about any runtime_pm_get():s from the irqchip functions:
Ulf and others are discussing with Thomas Gleixner about a more general
solution here.
But since it's a regression I gues
Hi Geert,
Thank you for the patch.
On Monday 15 February 2016 22:16:51 Geert Uytterhoeven wrote:
> Move the pm-rcar driver to drivers/soc/renesas/, so it can be shared
> between arm32 (R-Car H1 and Gen2) and arm64 (R-Car Gen3).
>
> Signed-off-by: Geert Uytterhoeven
Reviewed-by: Laurent Pinchar
On Wed, Feb 10, 2016 at 11:38 PM, Sergei Shtylyov
wrote:
> From: Ryo Kataoka
>
> Add the SSI pin groups to the R8A7794 PFC driver.
>
> [Sergei: fixed inconsistent alternate pin group naming, split SSI5/6 pin
> groups into data/control ones, moved SSI7 data B group to its proper place,
> fixed p
Hi Geert,
Thank you for the patch.
On Monday 15 February 2016 22:16:53 Geert Uytterhoeven wrote:
> Populate the SYSC PM domains from DT.
>
> Special cases, like PM domains containing CPU cores or SCUs, are
> handled by scanning the DT topology.
>
> The SYSCIER register value is derived from the
Hi Geert,
Thank you for the patch.
On Monday 15 February 2016 22:16:50 Geert Uytterhoeven wrote:
> The Renesas R-Car System Controller provides power management for the
> CPU cores and various coprocessors, following the generic PM domain
> bindings in Documentation/devicetree/bindings/power/powe
Quoting Geert Uytterhoeven (2016-02-15 04:39:37)
> Cfr. commit a9ec81f4ed5c05db ("serial: sh-sci: Drop the interface
> clock").
>
> Signed-off-by: Geert Uytterhoeven
> ---
> I plan to queue this up with the other clk-shmobile patches in
> clk-shmobile-for-v4.6 and send a pull request later.
Ack.
On Tuesday 16 February 2016 01:08:18 Laurent Pinchart wrote:
> On Monday 15 February 2016 22:16:50 Geert Uytterhoeven wrote:
> > The Renesas R-Car System Controller provides power management for the
> > CPU cores and various coprocessors, following the generic PM domain
> > bindings in Documentatio
On Sun, Feb 14, 2016 at 10:56:03PM +0300, Sergei Shtylyov wrote:
> The driver has the *default* case doing nothing in the *switch* statement
> with an integer expression -- remove it.
>
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Simon Horman
On Sun, Feb 14, 2016 at 10:56:33PM +0300, Sergei Shtylyov wrote:
> The driver often has the *default* cases doing nothing in the *switch*
> statements with the integer expressions -- remove them.
>
> Signed-off-by: Sergei Shtylyov
Reviewed-by: Simon Horman
On Mon, Feb 15, 2016 at 01:41:31PM +0100, Geert Uytterhoeven wrote:
> The example in the DT binding documentation uses the preliminary DT
> bindings for the r8a7795 MSTP clocks, which never went upstream.
> Update the example to use the DT bindings for the upstream Clock Pulse
> Generator / Module
On Wed, Feb 10, 2016 at 12:34:13AM +, Kuninori Morimoto wrote:
>
> Hi Eduardo, Simon
>
> > > > Hi Eduardo
> > > >
> > > > I'm sorry I didn't mention you.
> > > > Can you please check these patches ?
> > >
> > > Yes Morimoto, they are now on my todo list.
> >
> >
> > Applied first one.
>
arm64: r8a7795 INTC-EX support using RENESAS_IRQC
[PATCH 01/02] arm64: dts: r8a7795: Add INTC-EX device node
[PATCH 02/02] arm64: renesas: Enable RENESAS_IRQC
These two patches add the INTC-EX device node to the r8a7795 DTSI
file and selects RENESAS_IRQC to enable the irqchip driver. Those
two to
From: Magnus Damm
Add a single r8a7795 INTC-EX device node to support
external IRQ pins IRQ0 -> IRQ5.
Signed-off-by: Magnus Damm
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 15 +++
1 file changed, 15 insertions(+)
--- 0001/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ work/ar
From: Magnus Damm
Select RENESAS_IRQC for Arm64 SoCs from Renesas to enable
build of drivers/irqchip/irq-renesas-irqc.c.
Signed-off-by: Magnus Damm
---
arch/arm64/Kconfig.platforms |1 +
1 file changed, 1 insertion(+)
--- 0001/arch/arm64/Kconfig.platforms
+++ work/arch/arm64/Kconfig.plat
From: Magnus Damm
This patch is a prototype hack that can be used to test INTC-EX
using the IRQ2 signal on r8a7795 Salvator-X with a loop back
adapter.
The external loop back adapter is connected to EXIO_D and
connects pin 9 (IRQ2/GP2_02) and pin 26 (ExA22/GP2_06).
To test enable CONFIG_GPIO_SY
On xHCI controllers of R-Car Gen2 and Gen3, the AC64 bit (bit 0) of
HCCPARAMS1 is set to 1. However, these SoCs don't support 64-bit address
memory pointers. So, this driver should call dma_set_coherent_mask(dev,
DMA_BIT_MASK(32)) in xhci_gen_setup(). Otherwise, the xHCI controller
will be died aft
Hi Florian,
I have observed what appears to be a regression in the ravb ethernet driver
caused by d5c3d84657db ("net: phy: Avoid polling PHY with
PHY_IGNORE_INTERRUPTS").
When booting net-next configured with the ARM64 defconfig on the Renesas
r8a7795/salvator-x I see the following and the ravb i
On February 15, 2016 7:26:46 PM PST, Simon Horman wrote:
>Hi Florian,
>
>I have observed what appears to be a regression in the ravb ethernet
>driver
>caused by d5c3d84657db ("net: phy: Avoid polling PHY with
>PHY_IGNORE_INTERRUPTS").
>
>When booting net-next configured with the ARM64 defconfig on
Hi Florian,
On Mon, Feb 15, 2016 at 09:08:46PM -0800, Florian Fainelli wrote:
> On February 15, 2016 7:26:46 PM PST, Simon Horman wrote:
> >Hi Florian,
> >
> >I have observed what appears to be a regression in the ravb ethernet
> >driver
> >caused by d5c3d84657db ("net: phy: Avoid polling PHY wit
On Mon, Feb 15, 2016 at 10:48 PM, Simon Horman
wrote:
> Though the keyboard driver for GPIO buttons(gpio-keys) will continue to
> check for/support the legacy "gpio-key,wakeup" boolean property to
> enable gpio buttons as wakeup source, "wakeup-source" is the new
> standard binding.
>
> This patch
On 15.02.2016 21:38, Geert Uytterhoeven wrote:
Add the missing "cache-unified" and "cache-level" properties to the
Cortex-A57 cache-controller node.
Signed-off-by: Geert Uytterhoeven
---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas: r8a7795: Add L2
cache-controller nodes", aft
On 15.02.2016 21:38, Geert Uytterhoeven wrote:
Add a device node for the Cortex-A53 L2 cache-controller.
The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
32 KiB x 16 ways).
Signed-off-by: Geert Uytterhoeven
---
v3:
- Remaining part of "[PATCH v2 6/6] arm64: renesas:
Hi Dirk,
On Tue, Feb 16, 2016 at 7:44 AM, Dirk Behme wrote:
> On 15.02.2016 21:38, Geert Uytterhoeven wrote:
>> Add a device node for the Cortex-A53 L2 cache-controller.
>>
>> The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as
>> 32 KiB x 16 ways).
>>
>> Signed-off-by: Geert
From: Magnus Damm
Deprecate "renesas,channels-mask" and update the r8a7790 CMT example.
Signed-off-by: Magnus Damm
Acked-by: Geert Uytterhoeven
Acked-by: Laurent Pinchart
Acked-by: Rob Herring
---
Changes since V2:
- Added Acked-by from Rob
- Removed Tested-by tag from DT binding patch -
clocksource: sh_cmt: DT binding rework V3
[PATCH v3 01/06] devicetree: bindings: Remove sh7372 CMT binding
[PATCH v3 02/06] devicetree: bindings: R-Car Gen2 CMT0 and CMT1 bindings
[PATCH v3 03/06] devicetree: bindings: r8a73a4 and R-Car Gen2 CMT bindings
[PATCH v3 04/06] devicetree: bindings: Depr
From: Magnus Damm
Add documentation for new separate CMT0 and CMT1 DT compatible strings
for R-Car Gen2. These compat strings allow us to enable CMT1-specific
features in the driver. The old compat strings will be deprecated in
the not so distant future.
Signed-off-by: Magnus Damm
Acked-by: Gee
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