Hi Wolfram,
On Mon, Nov 5, 2018 at 7:08 PM Wolfram Sang wrote:
> > Is there any chance this can start to bite us in the future?
>
> Well, there is always a chance but to the best of our current knowledge,
> we can't see it for Gen3. And even then, we can still fix it.
>
> I was entering SDHI
Hi Geert,
> Is there any chance this can start to bite us in the future?
Well, there is always a chance but to the best of our current knowledge,
we can't see it for Gen3. And even then, we can still fix it.
I was entering SDHI hackfest with the attitude of representing the
hardware which means
Hi Geert,
Thanks for your feedback.
On 2018-11-05 11:32:15 +0100, Geert Uytterhoeven wrote:
> Hi Niklas,
>
> On Thu, Nov 1, 2018 at 12:26 AM Niklas Söderlund
> wrote:
> > This is the result of the SDHI hackathon for a possible solution to the
> > clock issue on early ES versions. It is based
> This is the result of the SDHI hackathon for a possible solution to the
> clock issue on early ES versions. It is based on the Gen2 solution where
> a row of the possible clock settings are ignored on the effected SoC+ES
> versions. The first row is not effected when reading settings left by
From: Niklas Söderlund
Hi Geert,
This is the result of the SDHI hackathon for a possible solution to the
clock issue on early ES versions. It is based on the Gen2 solution where
a row of the possible clock settings are ignored on the effected SoC+ES
versions. The first row is not effected
