Hi Rahul,
On 6 December 2013 21:26, Rahul Sharma rahul.sha...@samsung.com wrote:
Add support for pll2650xx in samsung pll file. This pll variant
is close to pll36xx but uses CON2 registers instead of CON1.
Aud_pll in Exynos5260 is pll2650xx and uses this code.
Signed-off-by: Rahul Sharma
Hi Rahul,
On 6 December 2013 21:26, Rahul Sharma rahul.sha...@samsung.com wrote:
From: Pankaj Dubey pankaj.du...@samsung.com
exynos5260 use pll2520xx and it has different bitfields
for P,M,S values as compared to pll2550xx. Support for
pll2520xx is added here.
This is a bit confusing to me.
Hi Arun,
From: Arjun.K.V arjun...@samsung.com
The patch adds cpufreq driver for exynos5420.
Signed-off-by: Arjun.K.V arjun...@samsung.com
Signed-off-by: Andrew Bresticker abres...@chromium.org
Signed-off-by: Arun Kumar K arun...@samsung.com
---
drivers/cpufreq/Kconfig.arm |
On Wed, Nov 06, 2013 at 10:27:49AM +0900, Jingoo Han wrote:
Change the phy provider used from the old usb phy specific to a new one
using the generic phy framework.
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Kamil Debski k.deb...@samsung.com
---
Exynos OHCI driver also uses Exynos
Hi Kukjin,
Lukasz Majewski wrote:
Hi Kukjin,
Hi,
Hi Kukjin,
The TMU device tree node definition for Exynos4x12 family of
SoCs.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
Reviewed-by: Bartlomiej Zolnierkiewicz
b.zolnier...@samsung.com
This patch proposes to remove the use of the IRQF_DISABLED flag
It's a NOOP since 2.6.35 and it will be removed one day.
Signed-off-by: Michael Opdenacker michael.opdenac...@free-electrons.com
Reviewed-by: Jingoo Han jg1@samsung.com
---
arch/arm/mach-s3c24xx/dma.c | 2 +-
On Monday, December 09, 2013 10:56 AM, Greg KH wrote:
On Wed, Nov 06, 2013 at 10:27:49AM +0900, Jingoo Han wrote:
Change the phy provider used from the old usb phy specific to a new one
using the generic phy framework.
Signed-off-by: Jingoo Han jg1@samsung.com
Cc: Kamil Debski
Hi Rafael,
On 04-12-2013 02:59, Lukasz Majewski wrote:
Hi Rafael,
This patch series introduces support for CPU overclocking technique
called Boost.
It is a follow up of a LAB governor proposal. Boost is a LAB
component:
On Thu, Dec 5, 2013 at 4:07 PM, Mark Brown broo...@kernel.org wrote:
On Tue, Dec 03, 2013 at 10:29:42AM +0100, Linus Walleij wrote:
So a suggested patch to support weak hogs would be interesting
to look at. Can you provide details on how you think this would
work?
Or should we be going and
Hi Mark,
On Fri, Dec 6, 2013 at 4:57 PM, Mark Brown broo...@kernel.org wrote:
On Fri, Dec 06, 2013 at 10:44:33AM +0530, Padma Venkat wrote:
This is done in your earlier patch ASoC: samsung: Ensure DMA data is
initialised for secondary DAI . Was it done on purpose or by mistake
in this
Does warm reset while activating SuperSpeed HUBs if the hub activate type
is HUB_RESET_RESUME.
When we do Suspend-to-RAM with (any one of the 16, 32, 64 Jetflash) transcend
USB 3.0 device connected on 3.0 port, during resume I noticed that the
XHCI controller has moved to sometimes RECOVERY,
Hi Naveen, Andrew,
Please see my comments inline.
On Tuesday 12 of November 2013 12:07:05 Naveen Krishna Chatradhi wrote:
Exynos5420 has 5 TMU channels, the TRIMINFO register is
misplaced for TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at
Hi Naveen,
On Tuesday 19 of November 2013 18:35:25 Naveen Krishna Chatradhi wrote:
Exynos5420 has 5 TMU channels, the TRIMINFO register is
misplaced for TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a contains data for TMU channel 4
Hi Naveen,
On Tuesday 19 of November 2013 18:34:51 Naveen Krishna Chatradhi wrote:
On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.
To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in
Hi Naveen,
On Tuesday 19 of November 2013 18:34:19 Naveen Krishna Chatradhi wrote:
This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are
Hi Vikas,
On Mon, Dec 9, 2013 at 5:59 PM, Vikas Sajjan vikas.saj...@linaro.org wrote:
few minor nits here. ;-)
Does warm reset while activating SuperSpeed HUBs if the hub activate type
is HUB_RESET_RESUME.
When we do Suspend-to-RAM with (any one of the 16, 32, 64 Jetflash) transcend
USB
On Fri, Dec 6, 2013 at 12:54 AM, Stephen Warren swar...@wwwdotorg.org wrote:
On 12/03/2013 02:29 AM, Linus Walleij wrote:
(skipped the conversation on weak hogs, we are on the same page
here, just waiting for someone to start working on it ...)
Related, I prefer to put /all/ static pinctrl
Hi Naveen,
On Tuesday 12 of November 2013 12:07:48 Naveen Krishna Chatradhi wrote:
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and
Hi Daniel,
On Thursday 21 of November 2013 02:21:24 Daniel Kurtz wrote:
These tables are all immutable, make them const to save 4416 bytes of RAM.
size arch/arm/mach-exynos/pmu.o
text data bss
848 4420 4 // before
5264 4 4
Add v4l2 controls to set desired profile for VP8 encoder.
Acceptable levels for VP8 encoder are
0: Version 0
1: Version 1
2: Version 2
3: Version 3
Signed-off-by: Pawel Osciak posc...@chromium.org
Signed-off-by: Kiran AVND avnd.ki...@samsung.com
Signed-off-by: Arun Kumar K arun...@samsung.com
---
Hi Arun,
Some comments below...
On 12/09/2013 02:16 PM, Arun Kumar K wrote:
Add v4l2 controls to set desired profile for VP8 encoder.
Acceptable levels for VP8 encoder are
0: Version 0
1: Version 1
2: Version 2
3: Version 3
Signed-off-by: Pawel Osciak posc...@chromium.org
Hi Daniel,
On Thursday 21 of November 2013 02:21:25 Daniel Kurtz wrote:
The restore functions do not modify the passed in struct sleep_save,
so that parameter can be const.
This allows us to pass in const struct. This allows us to use const
structs sleep_save to define system registers
Hi Sachin,
On Thursday 21 of November 2013 09:47:34 Sachin Kamat wrote:
Add CLK_SET_RATE_PARENT flag to be able to change the frequency
to desired value.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
drivers/clk/samsung/clk-exynos5250.c |3 ++-
1 file changed, 2
Hi Seung-Woo,
On Friday 22 of November 2013 14:21:08 Seung-Woo Kim wrote:
The SRC_MFC register was incorrect. This patch corrects it.
Signed-off-by: Seung-Woo Kim sw0312@samsung.com
---
drivers/clk/samsung/clk-exynos4.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Good
Hi,
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Monday, December 09, 2013 8:56 AM
Hi,
On Friday 06 December 2013 09:58 PM, Kamil Debski wrote:
Hi Kishon,
Thank you for the review.
From: Kishon Vijay Abraham I [mailto:kis...@ti.com]
Sent: Friday, December 06,
Hi,
This replaces the consumer init_data structures with a lookup table
that contains complete associations with the phys and their users,
removing the need for the phy drivers themselves to care about their
users even when not using DT.
The lookup method is copied from the way the gpio
The users of the old method are now converted to the new one.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
---
Documentation/phy.txt | 100 ++--
drivers/phy/phy-core.c | 46 ++---
Provide a complete association for the phy and it's user
(musb) with the new phy_lookup_table.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
---
arch/arm/mach-omap2/twl-common.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git
Removes the need for the phys to be aware of their users
even when not using DT. The method is copied from gpiolib.c.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
---
drivers/phy/phy-core.c | 91 -
include/linux/phy/phy.h | 48
Removes the need for the consumer drivers requesting the
phys to provide name for the phy. This should ease the use
of the framework considerable when using only one phy, which
is usually the case when except with USB, but it can also
be useful with multiple phys.
This will also reduce noise from
Replace string and port that are used as phy name
parameter for various functions with con_id which is
commonly used in other frameworks.
Signed-off-by: Heikki Krogerus heikki.kroge...@linux.intel.com
---
drivers/phy/phy-core.c | 22 ++
include/linux/phy/phy.h | 8
Hi Kukjin,
On Monday 25 of November 2013 12:15:08 Mark Brown wrote:
From: Mark Brown broo...@linaro.org
Rather than requiring each board to explicitly disable the SPI controllers
it is not using instead require boards to enable those that they are using.
This is less work overall since
On Mon, 9 Dec 2013, Vikas Sajjan wrote:
Does warm reset while activating SuperSpeed HUBs if the hub activate type
is HUB_RESET_RESUME.
When we do Suspend-to-RAM with (any one of the 16, 32, 64 Jetflash) transcend
USB 3.0 device connected on 3.0 port, during resume I noticed that the
XHCI
Hi Naveen,
On Tuesday 26 of November 2013 09:52:46 Naveen Krishna Chatradhi wrote:
For Exynos4 and Exynos5 SoCs from Samsung the i2c clock is based
on a fixed 66 MHz peripheral clock, and therefore is completely
independent of the cpu frequency.
Thus, registering for a CPU freq notifier is
Hi Tomasz,
Thank you for the reviews.
On Dec 9, 2013 5:15 AM, Tomasz Figa t.f...@samsung.com wrote:
Hi Daniel,
On Thursday 21 of November 2013 02:21:24 Daniel Kurtz wrote:
These tables are all immutable, make them const to save 4416 bytes of RAM.
size arch/arm/mach-exynos/pmu.o
Yuvaraj,
On Sun, Dec 8, 2013 at 10:38 PM, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
Commit 0c3de788 (ARM: dts: change status property of dwmmc nodes
for exynos5250) missed out handling the exynos5250 snow dts file.
Signed-off-by : Abhilash Kesavan a.kesa...@samsung.com
Signed-off-by:
On Tuesday 10 of December 2013 00:11:40 Daniel Kurtz wrote:
Hi Tomasz,
Thank you for the reviews.
On Dec 9, 2013 5:15 AM, Tomasz Figa t.f...@samsung.com wrote:
Hi Daniel,
On Thursday 21 of November 2013 02:21:24 Daniel Kurtz wrote:
These tables are all immutable, make them const
Yuvaraj,
On Sun, Dec 8, 2013 at 10:38 PM, Yuvaraj Kumar C D yuvaraj...@gmail.com wrote:
Commit 64c138a (ARM: dts: Move fifo-depth property from exynos5250
board dts) missed out handling the exynos5250 snow dts file.
Deletes the fifo-depth property, as this property has been moved to
SOC
Hi Tomasz,
On 9 December 2013 19:01, Tomasz Figa t.f...@samsung.com wrote:
Hi Sachin,
On Thursday 21 of November 2013 09:47:34 Sachin Kamat wrote:
Add CLK_SET_RATE_PARENT flag to be able to change the frequency
to desired value.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
Hi Naveen,
On Tuesday 26 of November 2013 09:56:17 Naveen Krishna Chatradhi wrote:
This patch adds new compatible to support HSI2C module on Exynos5260
HSI2C module on Exynos5260 needs to be reset during during initialization.
Signed-off-by: Naveen Krishna Chatradhi ch.nav...@samsung.com
Hi Naveen,
On Friday 22 of November 2013 11:44:11 Naveen Krishna Chatradhi wrote:
fifo_depth of the HSI2C is not constant
Exynos5420 and Exynos5250 supports fifo_depth of 64bytes
Exynos5260 supports fifo_depth of 16bytes
This patch configures the fifo_depth based on HSI2C modules version.
Hi Vyacheslav, Tarek,
On Tuesday 26 of November 2013 12:58:06 Vyacheslav Tyrtov wrote:
From: Tarek Dakhran t.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
Signed-off-by: Tarek Dakhran
Hi Sachin,
On Thursday 28 of November 2013 16:08:01 Sachin Kamat wrote:
Arndale Octa board is based on Exynos5420 SoC. This patch
adds the basic support required for booting it through DT.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/Makefile
Hi Heiko,
On Tuesday 03 of December 2013 16:23:09 Heiko Stübner wrote:
Starting with the s3c2443 the s3c24xx series got a new clock tree
compared to the previous s3c24xx socs. This binding describes the
clock controller found in the s3c2443, s3c2416 and s3c2450 socs.
Signed-off-by: Heiko
On Mon, Dec 09, 2013 at 11:22:44AM +0100, Linus Walleij wrote:
On Thu, Dec 5, 2013 at 4:07 PM, Mark Brown broo...@kernel.org wrote:
Or should we be going and applying the default state to all devices on
init without worrying about a driver appearing?
That doesn't really work: if you have
Hi Mark,
On Mon, Dec 9, 2013 at 5:30 PM, Padma Venkat padma@gmail.com wrote:
Hi Mark,
On Fri, Dec 6, 2013 at 4:57 PM, Mark Brown broo...@kernel.org wrote:
On Fri, Dec 06, 2013 at 10:44:33AM +0530, Padma Venkat wrote:
This is done in your earlier patch ASoC: samsung: Ensure DMA data is
On Mon, Dec 09, 2013 at 05:30:47PM +0530, Padma Venkat wrote:
This is required only after your changes because in dmaengine we are
requesting the dma channel statically but in mainline(with samsung
proprietary ops) we are requesting the dma channel at run time during
playback or capture.
OK,
Hi Heiko,
On Tuesday 03 of December 2013 16:24:11 Heiko Stübner wrote:
This converts the mentioned platforms to use the newly introduced driver
for the common clock framework for them.
With this the whole legacy clock structure can go away too.
Signed-off-by: Heiko Stuebner
Hi Heiko,
On Tuesday 03 of December 2013 16:19:57 Heiko Stübner wrote:
Resurrecting this series again after to much time.
Changed is the pll registration to follow the new system and getting the
external clocks from dt fixed-rate clocks.
Hopefully I did address all comments received for
On Fri, Dec 06, 2013 at 10:44:19AM +0530, Padma Venkat wrote:
I couldn't test this patch set due to some crash in recent kernel in
dmaengine_unmap_put. I think this unmap support is not yet implemented
for pl330 driver. It is mentioned in the commit dmaengine: prepare
for generic 'unmap'
Hi Mark,
On Thu, Dec 5, 2013 at 5:15 PM, Mark Brown broo...@kernel.org wrote:
On Thu, Dec 05, 2013 at 04:20:03PM +0530, Padma Venkat wrote:
On Thu, Nov 28, 2013 at 5:23 PM, Mark Brown broo...@kernel.org wrote:
OK, so we can probably just reinitialise the dmaengine data after we
reset it?
On Mon, Dec 09, 2013 at 11:22:39PM +0530, Padma Venkat wrote:
I think this is what you are concern about why it is not working as-is.
OK, makes sense - thanks!
signature.asc
Description: Digital signature
On Mon, Dec 09, 2013 at 10:24:52AM -0500, Alan Stern wrote:
On Mon, 9 Dec 2013, Vikas Sajjan wrote:
Does warm reset while activating SuperSpeed HUBs if the hub activate type
is HUB_RESET_RESUME.
When we do Suspend-to-RAM with (any one of the 16, 32, 64 Jetflash)
transcend
USB 3.0
Hi Yadwinder, Sachin,
On Friday 15 of November 2013 17:11:28 Sachin Kamat wrote:
From: Yadwinder Singh Brar yadi.b...@samsung.com
This patch introduces a common ASV (Adaptive Supply Voltage) basic framework
for samsung SoCs. It provides common APIs (to be called by users to get ASV
values
On 12/10/13 01:37, Tomasz Figa wrote:
Hi Sachin,
On Thursday 28 of November 2013 16:08:01 Sachin Kamat wrote:
Arndale Octa board is based on Exynos5420 SoC. This patch
adds the basic support required for booting it through DT.
Signed-off-by: Sachin Kamatsachin.ka...@linaro.org
---
On 12/10/13 01:34, Tomasz Figa wrote:
Hi Vyacheslav, Tarek,
On Tuesday 26 of November 2013 12:58:06 Vyacheslav Tyrtov wrote:
From: Tarek Dakhrant.dakh...@samsung.com
The EXYNOS5410 clocks are statically listed and registered
using the Samsung specific common clock helper functions.
On 12/10/13 01:19, Doug Anderson wrote:
Yuvaraj,
On Sun, Dec 8, 2013 at 10:38 PM, Yuvaraj Kumar C Dyuvaraj...@gmail.com wrote:
Commit 64c138a (ARM: dts: Move fifo-depth property from exynos5250
board dts) missed out handling the exynos5250 snow dts file.
Deletes the fifo-depth property, as
On 12/10/13 01:16, Doug Anderson wrote:
Yuvaraj,
On Sun, Dec 8, 2013 at 10:38 PM, Yuvaraj Kumar C Dyuvaraj...@gmail.com wrote:
Commit 0c3de788 (ARM: dts: change status property of dwmmc nodes
for exynos5250) missed out handling the exynos5250 snow dts file.
Signed-off-by : Abhilash
On 12/10/13 01:15, Tomasz Figa wrote:
On Tuesday 10 of December 2013 00:11:40 Daniel Kurtz wrote:
Hi Tomasz,
Thank you for the reviews.
On Dec 9, 2013 5:15 AM, Tomasz Figat.f...@samsung.com wrote:
Hi Daniel,
On Thursday 21 of November 2013 02:21:24 Daniel Kurtz wrote:
These tables are
On 12/10/13 00:23, Tomasz Figa wrote:
Hi Kukjin,
Hi,
On Monday 25 of November 2013 12:15:08 Mark Brown wrote:
From: Mark Brownbroo...@linaro.org
Rather than requiring each board to explicitly disable the SPI controllers
it is not using instead require boards to enable those that they are
On 11/19/13 22:05, Naveen Krishna Chatradhi wrote:
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and the second
clock to access the
On 12/09/13 18:02, Michael Opdenacker wrote:
This patch proposes to remove the use of the IRQF_DISABLED flag
It's a NOOP since 2.6.35 and it will be removed one day.
Signed-off-by: Michael Opdenackermichael.opdenac...@free-electrons.com
Reviewed-by: Jingoo Hanjg1@samsung.com
---
On 12/09/13 13:38, Michael Opdenacker wrote:
This removes the SAMSUNG_GPIOLIB_4BIT Kconfig parameter,
which was no longer used anywhere in the source code
and Makefiles.
Signed-off-by: Michael Opdenackermichael.opdenac...@free-electrons.com
Reviewed-by: Jingoo Hanjg1@samsung.com
---
On 12/06/13 20:58, Linus Walleij wrote:
On Fri, Dec 6, 2013 at 10:31 AM, Linus Walleijlinus.wall...@linaro.org wrote:
Hi Linus,
This isolates the custom S3C24xx GPIO definition table to
linux/platform_data/gpio-samsung-s3x24xx.h
Maybe I'm too trigger happy. I'll send a combined series
On 12/05/13 20:36, Tomasz Figa wrote:
Hi Sachin,
On Monday 02 of December 2013 16:41:42 Sachin Kamat wrote:
Added high speed I2C nodes to Exynos5420 DT file.
Signed-off-by: Sachin Kamatsachin.ka...@linaro.org
---
Changes since v1:
Changed the node name to i2c as suggested by Tomasz Figa.
---
On 12/05/13 18:44, Sachin Kamat wrote:
Added regulator entries to Exynos5420 SMDK board.
Signed-off-by: Sachin Kamatsachin.ka...@linaro.org
---
Changes since v1:
Changed node name
---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 216 +
1 file changed, 216
On 11/30/13 02:29, Tomasz Figa wrote:
On Friday 29 of November 2013 17:04:52 Sachin Kamat wrote:
Added missing clock frequency property to CPU node to avoid
boot time warnings.
Signed-off-by: Sachin Kamatsachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5250.dtsi |2 ++
1 file
Hi Kukjin,
On Tuesday 10 of December 2013 06:15:08 Kukjin Kim wrote:
On 11/19/13 22:05, Naveen Krishna Chatradhi wrote:
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes
On 11/27/13 18:15, Sachin Kamat wrote:
The minimum recommended ARM voltage for Exynos5250 at 200MHz
on Arndale board is 0.9125V. Update accordingly.
Signed-off-by: Sachin Kamatsachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5250-arndale.dts |2 +-
1 file changed, 1 insertion(+), 1
On 11/27/13 18:14, Sachin Kamat wrote:
Though the default value is 1, add it explicitly to avoid
unnecessary boot warnings and for consistency.
Signed-off-by: Sachin Kamatsachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5250-arndale.dts |2 ++
1 file changed, 2 insertions(+)
diff
Hi,
On Mon, Dec 9, 2013 at 1:07 PM, Kukjin Kim kgene@samsung.com wrote:
On 12/10/13 00:23, Tomasz Figa wrote:
Hi Kukjin,
Hi,
On Monday 25 of November 2013 12:15:08 Mark Brown wrote:
From: Mark Brownbroo...@linaro.org
Rather than requiring each board to explicitly disable the SPI
Hi Arun,
On Mon, Dec 9, 2013 at 10:16 PM, Arun Kumar K arun...@samsung.com wrote:
Add v4l2 controls to set desired profile for VP8 encoder.
Acceptable levels for VP8 encoder are
0: Version 0
1: Version 1
2: Version 2
3: Version 3
Signed-off-by: Pawel Osciak posc...@chromium.org
Sorry,
Hi,
On Mon, Nov 25, 2013 at 4:15 AM, Mark Brown broo...@kernel.org wrote:
From: Mark Brown broo...@linaro.org
Rather than requiring each board to explicitly disable the SPI controllers
it is not using instead require boards to enable those that they are using.
This is less work overall since
Hi Kamil,
Same USB2.0 PHY may be used by several HCDs, for example EHCI and OHCI.
Consider the situation, when EHCI stops using the PHY and calls power_off,
then OHCI becomes non-operational. In other words, PHY power_on and
power_off calls must be balanced.
Shall we handle it in your driver?
Hi Lukasz,
Thank you for the review.
On Mon, Dec 9, 2013 at 1:53 PM, Lukasz Majewski l.majew...@samsung.com wrote:
Hi Arun,
From: Arjun.K.V arjun...@samsung.com
The patch adds cpufreq driver for exynos5420.
Signed-off-by: Arjun.K.V arjun...@samsung.com
Signed-off-by: Andrew Bresticker
Hi Hans,
Thanks for the review.
On Mon, Dec 9, 2013 at 6:52 PM, Hans Verkuil hverk...@xs4all.nl wrote:
Hi Arun,
Some comments below...
On 12/09/2013 02:16 PM, Arun Kumar K wrote:
Add v4l2 controls to set desired profile for VP8 encoder.
Acceptable levels for VP8 encoder are
0: Version 0
Hi Pawel,
On Tue, Dec 10, 2013 at 6:21 AM, Pawel Osciak posc...@chromium.org wrote:
Hi Arun,
On Mon, Dec 9, 2013 at 10:16 PM, Arun Kumar K arun...@samsung.com wrote:
Add v4l2 controls to set desired profile for VP8 encoder.
Acceptable levels for VP8 encoder are
0: Version 0
1: Version 1
Hello Tomasz,
On 9 December 2013 22:01, Tomasz Figa t.f...@samsung.com wrote:
Hi Naveen,
On Friday 22 of November 2013 11:44:11 Naveen Krishna Chatradhi wrote:
fifo_depth of the HSI2C is not constant
Exynos5420 and Exynos5250 supports fifo_depth of 64bytes
Exynos5260 supports
Hi Arun,
On 10 December 2013 10:15, Arun Kumar K arunkk.sams...@gmail.com wrote:
Hi Pawel,
On Tue, Dec 10, 2013 at 6:21 AM, Pawel Osciak posc...@chromium.org wrote:
Hi Arun,
Ok will make the change in next version.
While at it also update the patch subject appropriately.
--
With warm
Hi Sachin,
On Tue, Dec 10, 2013 at 10:38 AM, Sachin Kamat sachin.ka...@linaro.org wrote:
Hi Arun,
On 10 December 2013 10:15, Arun Kumar K arunkk.sams...@gmail.com wrote:
Hi Pawel,
On Tue, Dec 10, 2013 at 6:21 AM, Pawel Osciak posc...@chromium.org wrote:
Hi Arun,
Ok will make the change
Hi Sarah,
On Mon, Dec 9, 2013 at 11:54 PM, Sarah Sharp
sarah.a.sh...@linux.intel.com wrote:
On Mon, Dec 09, 2013 at 10:24:52AM -0500, Alan Stern wrote:
On Mon, 9 Dec 2013, Vikas Sajjan wrote:
Does warm reset while activating SuperSpeed HUBs if the hub activate type
is HUB_RESET_RESUME.
Hi Alan,
On Mon, Dec 9, 2013 at 8:54 PM, Alan Stern st...@rowland.harvard.edu wrote:
On Mon, 9 Dec 2013, Vikas Sajjan wrote:
Does warm reset while activating SuperSpeed HUBs if the hub activate type
is HUB_RESET_RESUME.
When we do Suspend-to-RAM with (any one of the 16, 32, 64 Jetflash)
Added PMIC node to Arndale-Octa board.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 220 +
1 file changed, 220 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
This patchset does a little clean up of the existing code (linux-soc-thermal)
1. [v11] thermal: samsung: replace inten_ bit fields with intclr_
2. [v11] thermal: samsung: change base_common to more meaningful base_second
adds support for Exynos5420 in the driver and (linux-soc-thermal)
3.
This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
to configure intclr related registers.
Description of H/W:
The offset for the
On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.
To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the reg property of the node.
As per Amit's suggestion, this patch changes the
S2MPS11 voltage regulator is commonly used on the latest Exynos
boards like SMDK5420, Arndale-Octa, etc. Hence it makes sense to
enable it like S5M8767A voltage regulator.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
---
arch/arm/configs/exynos_defconfig |1 +
1 file changed, 1
Exynos5420 has 5 TMU channels, the TRIMINFO register is
misplaced for TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2
This patch
1 Adds the neccessary
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
Signed-off-by: Leela Krishna
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