Hi Bjorn, ,
On 11/12/2013 19:32, Bjorn Helgaas wrote:
> If this looks reasonable, I'll merge it via the PCI tree for v3.13.
>
> Bjorn
>
>
> MAINTAINERS: Add DesignWare, i.MX6, Armada, R-Car PCI host maintainers
>
> Add entries for PCI host controller drivers in drivers/pci/host/.
>
> Signed-o
>> ...although, the spec says that it does not wait for the port resets
>> to complete. As far as I can see re-issuing a warm reset and waiting
>> is the only way to guarantee the core times the recovery. Presumably
>> the portstatus debounce in hub_activate() mitigates this, but that
>> 100ms is
Hi Bjorn,
On Wed, Dec 11, 2013 at 11:32:37AM -0700, Bjorn Helgaas wrote:
> +PCI DRIVER FOR IMX6
> +M: Shawn Guo
Thanks for the nomination. But I think a better person for this
position would be Richard Zhu (copied). He knows
the driver and controller much better than myself, and most import
ARM_PATCH_PHYS_VIRT and AUTO_ZRELADDR have been enabled as default configs
to S5P64X0 platforms.
Introduction of PHYS_VIRT config as default would enable phy-to-virt and
virt-to-phy translation function at boot and module loading time
and enforce dynamic reallocation of memory. AUTO_ZRELADDR confi
> -Original Message-
> From: Jingoo Han [mailto:jg1@samsung.com]
> Sent: Thursday, December 12, 2013 3:55 AM
> To: 'Bjorn Helgaas'; linux-...@vger.kernel.org
> Cc: linux-ker...@vger.kernel.org; linux-arm-ker...@lists.infradead.org;
> linux-te...@vger.kernel.org; linux...@vger.kernel.org
Hi Tomasz and Doug,
Thanks for the review.
On Thu, Dec 12, 2013 at 6:00 AM, Doug Anderson wrote:
> Tomasz,
>
> On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa wrote:
>> 2013/12/12 Doug Anderson :
>>> This does match what's done in exynos4 and exynos5420 and it's not
>>> terrible. I'm always a fan
The CLK_GATE_IP_ACP register offset is incorrectly listed.
Fix this and the register ordering as well.
Signed-off-by: Abhilash Kesavan
---
drivers/clk/samsung/clk-exynos5250.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/c
Fix wrong clock number in mdma0 node.
Signed-off-by: Abhilash Kesavan
---
arch/arm/boot/dts/exynos5250.dtsi |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5250.dtsi
b/arch/arm/boot/dts/exynos5250.dtsi
index 9db5047..177becd 100644
--- a/arch/arm/b
Adds gate clock for MDMA0 on Exynos5250 SoC.
Signed-off-by: Abhilash Kesavan
---
.../devicetree/bindings/clock/exynos5250-clock.txt |2 ++
drivers/clk/samsung/clk-exynos5250.c |5 -
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/b
Hi Doug,
On Thu, Dec 12, 2013 at 5:27 AM, Doug Anderson wrote:
> Abhliash,
>
> On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan
> wrote:
>> Fix the following warning message:
>> [ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399
>> irq_create_mapping+0xe4/0xfc()
>> [ 2921.679
Hi Tomasz,
On Wed, Dec 11, 2013 at 5:54 PM, Tomasz Figa wrote:
> Hi Abhilash,
>
> On Wednesday 11 of December 2013 17:27:07 Abhilash Kesavan wrote:
>> Following messages are observed when unused PMIC clocks are being
>> disabled during boot-up:
>> [ 2921.969560] BUG: scheduling while atomic: swap
Hi Tomasz,
On Wed, Dec 11, 2013 at 6:11 PM, Tomasz Figa wrote:
> Hi Abhilash,
>
> On Wednesday 11 of December 2013 17:27:04 Abhilash Kesavan wrote:
>> Patch 1 prevents the gating of sysreg clock on Exynos5250.
>> Patch 2 is a re-send of an earlier patch.
>> (http://www.spinics.net/lists/linux-sam
Hi Tomasz,
On Wed, Dec 11, 2013 at 5:59 PM, Tomasz Figa wrote:
> Hi Abhilash,
>
> [dropping invalid address of DT mailing list]
>
> Please see my comments inline.
>
> On Wednesday 11 of December 2013 17:27:06 Abhilash Kesavan wrote:
>> For the six local power blocks - MFC, DISP1, GSC, MAU, G3D an
On Sunday, December 08, 2013 01:41:08 PM Borislav Petkov wrote:
> On Sun, Dec 08, 2013 at 01:34:36AM +0100, Rafael J. Wysocki wrote:
> > On Saturday, December 07, 2013 04:24:09 PM Paul Bolle wrote:
> > > On Sat, 2013-12-07 at 12:01 +0100, Bjørn Mork wrote:
> > > > Sorry to be making noise here agai
Tomasz,
On Wed, Dec 11, 2013 at 4:13 PM, Tomasz Figa wrote:
> 2013/12/12 Doug Anderson :
>> This does match what's done in exynos4 and exynos5420 and it's not
>> terrible. I'm always a fan of actually specifying clocks properly and
>> that's more possible now using the syscon stuff (see Leela Kr
2013/12/12 Doug Anderson :
> Abhilash,
>
> On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan
> wrote:
>> The sysreg (system register) generates control signals for various blocks
>> like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
>> at boot-up.
>>
>> Signed-off-by: Abhi
2013/12/11 Doug Anderson :
> Leela Krishna,
>
> On Wed, Dec 11, 2013 at 4:22 AM, Leela Krishna Amudala
> wrote:
>> Hi,
>>
>> As I was in travel not accessed my mails.
>>
>> I'll try to post next version of this series tomorrow addressing
>> Sylwester's comments.
>
> It's completely up to you (and
Abhliash,
On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan wrote:
> Fix the following warning message:
> [ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399
> irq_create_mapping+0xe4/0xfc()
> [ 2921.679907] irq_create_mapping(, b) called with NULL domain
> [ 2921.685462] Modules
Abhilash,
On Wed, Dec 11, 2013 at 3:57 AM, Abhilash Kesavan wrote:
> The sysreg (system register) generates control signals for various blocks
> like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
> at boot-up.
>
> Signed-off-by: Abhilash Kesavan
> ---
> drivers/clk/samsu
On Wed, Dec 11, 2013 at 11:32:37AM -0700, Bjorn Helgaas wrote:
> If this looks reasonable, I'll merge it via the PCI tree for v3.13.
>
> Bjorn
>
>
> MAINTAINERS: Add DesignWare, i.MX6, Armada, R-Car PCI host maintainers
>
> Add entries for PCI host controller drivers in drivers/pci/host/.
>
>
On Wed, Dec 11, 2013 at 2:51 PM, Dan Williams wrote:
> On Wed, Dec 11, 2013 at 11:36 AM, Sarah Sharp
> wrote:
>> On Wed, Dec 11, 2013 at 11:00:13AM -0800, Julius Werner wrote:
>>> > I don't know what you mean by "fails". The system goes to sleep and
>>> > then later on wakes up, doesn't it?
>>>
Leela Krishna,
On Wed, Dec 11, 2013 at 4:22 AM, Leela Krishna Amudala
wrote:
> Hi,
>
> As I was in travel not accessed my mails.
>
> I'll try to post next version of this series tomorrow addressing
> Sylwester's comments.
It's completely up to you (and Wim), of course. ...but if it were me
I wo
On Wed, Dec 11, 2013 at 11:36 AM, Sarah Sharp
wrote:
> On Wed, Dec 11, 2013 at 11:00:13AM -0800, Julius Werner wrote:
>> > I don't know what you mean by "fails". The system goes to sleep and
>> > then later on wakes up, doesn't it?
>> >
>> > Do you mean that the Jetflash device gets disconnected
On 12/10/13 23:26, Vyacheslav Tyrtov wrote:
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches add new platform description, support of clock controller and device
tree for Exynos 5410.
Dual cluster suppor
On Thursday, December 12, 2013 3:43 AM, Bjorn Helgaas wrote:
> On Wed, Dec 11, 2013 at 11:32:37AM -0700, Bjorn Helgaas wrote:
> > If this looks reasonable, I'll merge it via the PCI tree for v3.13.
>
> And I see Mohit's patch [1] to update the DesignWare entry:
>
> +PCIE DRIVER FOR SYNOPSIS DESIG
From: Mark Brown
There is a 16.934MHz fixed rate clock connected to MCLK1 on the CODEC, add
this to the device tree bindings.
Signed-off-by: Mark Brown
---
arch/arm/boot/dts/exynos5250-smdk5250.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5250-smdk52
On Wed, Dec 11, 2013 at 11:00:13AM -0800, Julius Werner wrote:
> > I don't know what you mean by "fails". The system goes to sleep and
> > then later on wakes up, doesn't it?
> >
> > Do you mean that the Jetflash device gets disconnected when the system
> > wakes up? That's _supposed_ to happen u
> I don't know what you mean by "fails". The system goes to sleep and
> then later on wakes up, doesn't it?
>
> Do you mean that the Jetflash device gets disconnected when the system
> wakes up? That's _supposed_ to happen under those circumstances.
> When hub_activate() sees HUB_RESET_RESUME, al
[+cc Mohit]
On Wed, Dec 11, 2013 at 11:32:37AM -0700, Bjorn Helgaas wrote:
> If this looks reasonable, I'll merge it via the PCI tree for v3.13.
And I see Mohit's patch [1] to update the DesignWare entry:
+PCIE DRIVER FOR SYNOPSIS DESIGNWARE CONTROLLER
+M: Mohit Kumar
+M: Jingoo Han
+L
If this looks reasonable, I'll merge it via the PCI tree for v3.13.
Bjorn
MAINTAINERS: Add DesignWare, i.MX6, Armada, R-Car PCI host maintainers
Add entries for PCI host controller drivers in drivers/pci/host/.
Signed-off-by: Bjorn Helgaas
---
MAINTAINERS | 31 +
On Tue, 10 Dec 2013, Vikas Sajjan wrote:
> > Finally, I don't see why you put this in hub_activate(). Isn't it more
> > closely connected with the reset-resume procedure for the child device?
>
>
> I was trying to add a FIX in usb_port_resume(), but in our case we
> have CONFIG_USB_DEFAULT_PERS
On Thu, Dec 05, 2013 at 01:29:35PM +0100, Kamil Debski wrote:
> Change the used phy driver to the new Exynos USB phy driver that uses the
> generic phy framework.
>
> Signed-off-by: Kamil Debski
> Signed-off-by: Kyungmin Park
> ---
> .../devicetree/bindings/usb/samsung-hsotg.txt |4 +++
Hi Abhilash,
On Wednesday 11 of December 2013 17:27:04 Abhilash Kesavan wrote:
> Patch 1 prevents the gating of sysreg clock on Exynos5250.
> Patch 2 is a re-send of an earlier patch.
> (http://www.spinics.net/lists/linux-samsung-soc/msg15485.html)
> Patches 3 and 4 are fixes for MAX77686 on Exyno
Hi Abhilash,
[dropping invalid address of DT mailing list]
Please see my comments inline.
On Wednesday 11 of December 2013 17:27:06 Abhilash Kesavan wrote:
> For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
> the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
>
Hi Abhilash,
On Wednesday 11 of December 2013 17:27:07 Abhilash Kesavan wrote:
> Following messages are observed when unused PMIC clocks are being
> disabled during boot-up:
> [ 2921.969560] BUG: scheduling while atomic: swapper/0/1/0x0002
> [ 2921.974080] Modules linked in:
> [ 2921.977120] C
Hi,
As I was in travel not accessed my mails.
I'll try to post next version of this series tomorrow addressing
Sylwester's comments.
Best Wishes,
Leela Krishna.
On Sun, Dec 8, 2013 at 7:20 AM, Sylwester Nawrocki
wrote:
> Hi Tomasz,
>
>
> On 12/07/2013 01:57 AM, Tomasz Figa wrote:
>>
>> On Frid
Add intial PMU settings for exynos5420. This is required for
future S2R and Switching support.
Signed-off-by: Thomas Abraham
Signed-off-by: Abhilash Kesavan
---
arch/arm/mach-exynos/include/mach/regs-pmu.h | 82
arch/arm/mach-exynos/pmu.c | 106
Patch 1 prevents the gating of sysreg clock on Exynos5250.
Patch 2 is a re-send of an earlier patch.
(http://www.spinics.net/lists/linux-samsung-soc/msg15485.html)
Patches 3 and 4 are fixes for MAX77686 on Exynos5250 based Snow
board (boot-up issues).
Patch 5 implements a power-off call-back for Ex
Following messages are observed when unused PMIC clocks are being
disabled during boot-up:
[ 2921.969560] BUG: scheduling while atomic: swapper/0/1/0x0002
[ 2921.974080] Modules linked in:
[ 2921.977120] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
3.13.0-rc1-00018-g8465d57 #27
[ 2921.984772] []
Fix the following warning message:
[ 2921.671238] WARNING: CPU: 0 PID: 1 at kernel/irq/irqdomain.c:399
irq_create_mapping+0xe4/0xfc()
[ 2921.679907] irq_create_mapping(, b) called with NULL domain
[ 2921.685462] Modules linked in:
[ 2921.688498] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
3.13.0-rc
For the six local power blocks - MFC, DISP1, GSC, MAU, G3D and ISP
the respective CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers need
to be low initially for normal mode on Exynos5250.
Also fix the corresponding AFTR and LPA configurations.
Signed-off-by: Abhilash Kesavan
---
arch/arm/mach-exyn
From: Olof Johansson
Add pm_power_off callback function for exynos5250 to make soft
power off work properly.
Signed-off-by: Abhilash Kesavan
Signed-off-by: Olof Johansson
---
arch/arm/mach-exynos/include/mach/regs-pmu.h |3 +++
arch/arm/mach-exynos/pmu.c | 20 +
The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi etc. However, it gets disabled as an unused clock
at boot-up.
Signed-off-by: Abhilash Kesavan
---
drivers/clk/samsung/clk-exynos5250.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
di
Hi Rahul,
Please see my comments inline.
On Friday 06 of December 2013 21:26:28 Rahul Sharma wrote:
> Samsung CCF helper functions do not provide support to
> register multiple Clock Providers for a given SoC. Due to
> this limitation SoC platforms are not able to use these
> helpers for register
From: Young-Gun Jang
Adds CMU virtual addresses for exynos5260.
Change-Id: Ia4f4eda96187d8d9e1edfc1a6b025af56d3bc43e
Signed-off-by: Young-Gun Jang
Signed-off-by: Vikas Sajjan
---
arch/arm/mach-exynos/common.c | 65 ++
arch/arm/mach-exynos/include/mach/
Adds initial PMU support for Exynos5260
Following are the changes done
--
1) Added initial PMU support for exynos5260
2) Added exynos5260_iodesc for mapping 5260 specific SFRs. We modified
exynos5_map_io so that in case of exynos5260 only exynos5260_iodesc can
be init
1) Added initial PMU support for exynos5260
2) Added exynos5260_iodesc for mapping 5260 specific SFRs. We modified
exynos5_map_io so that in case of exynos5260 only exynos5260_iodesc can
be initialized.
3) Added new macros for WAKEUP MASK for 5260, and modified exynos_pm_drvinit
accordingly.
4)
On 11/12/13 10:54, Kishon Vijay Abraham I wrote:
> On Wednesday 27 November 2013 06:56 PM, Tomasz Stanislawski wrote:
>> > Hello everyone,
>> > The Samsung SoCs from Exynos family are enhanced with a bunch of switches
>> > dedicated for IP blocks. Those switches are called PHYs in Exynos
>> > speci
On 12/10/2013 08:40 PM, Kevin Hilman wrote:
Vyacheslav Tyrtov writes:
The series of patches represent support of Exynos 5410 SoC
The Exynos 5410 is the first Samsung SoC based on bigLITTLE architecture
Patches add new platform description, support of clock controller and device
tree for Exyn
Hi,
On Wednesday 27 November 2013 06:56 PM, Tomasz Stanislawski wrote:
> Hello everyone,
> The Samsung SoCs from Exynos family are enhanced with a bunch of switches
> dedicated for IP blocks. Those switches are called PHYs in Exynos
> specification. They are usually controlled by a single bit in a
Hi again,
On Wed, Dec 11, 2013 at 02:02:43PM +0530, Vivek Gautam wrote:
> On Wed, Dec 11, 2013 at 1:39 PM, Heikki Krogerus
> wrote:
> > On Wed, Dec 11, 2013 at 12:08:04PM +0530, Vivek Gautam wrote:
> >> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
> >> > I think "setup" instead of "tune" is m
Hi Kishon,
On Wed, Dec 11, 2013 at 1:47 PM, Kishon Vijay Abraham I wrote:
> On Wednesday 11 December 2013 12:08 PM, Vivek Gautam wrote:
>> Hi,
>>
>>
>> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
>> wrote:
>>> Hi,
>>
>> Thanks for reviewing this.
>>
>>>
>>> On Tue, Dec 10, 2013 at 04:25:23
Hi,
On Wed, Dec 11, 2013 at 1:39 PM, Heikki Krogerus
wrote:
> Hi,
>
> On Wed, Dec 11, 2013 at 12:08:04PM +0530, Vivek Gautam wrote:
>> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
>> > I think "setup" instead of "tune" is much more clear and reusable.
>>
>> I think "setup" will look more lik
On Wednesday 11 December 2013 12:08 PM, Vivek Gautam wrote:
> Hi,
>
>
> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
> wrote:
>> Hi,
>
> Thanks for reviewing this.
>
>>
>> On Tue, Dec 10, 2013 at 04:25:23PM +0530, Vivek Gautam wrote:
>>> Some PHY controllers may need to tune PHY post-initi
Hi,
On Wed, Dec 11, 2013 at 12:08:04PM +0530, Vivek Gautam wrote:
> On Tue, Dec 10, 2013 at 7:31 PM, Heikki Krogerus
> > I think "setup" instead of "tune" is much more clear and reusable.
>
> I think "setup" will look more like first time setting up the phy,
> which is rather served by "init" cal
55 matches
Mail list logo
