This patch adds regulator-haptic device node controlled by regulator.
Signed-off-by: Jaewon Kim
Reviewed-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos3250-monk.dts |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-monk.dts
b/arch/arm/boot/dts/exynos3250
This patch series adds regulator-haptic device tree in rinato and monk boards.
The regulator-haptic has haptic motor and it is controlled by
voltage of regulator via force feedback framework.
regualtor-haptic driver merged at linux-next
ref : https://lkml.org/lkml/2014/12/17/477
Jaewon Kim (2):
This patch adds regulator-haptic device node controlled by regulator.
Signed-off-by: Jaewon Kim
Reviewed-by: Chanwoo Choi
---
arch/arm/boot/dts/exynos3250-rinato.dts |7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts
b/arch/arm/boot/dts/exynos
Hi Sylwester,
I'm so sorry. I miss adding the version to patch[10-12].
- [PATCH 10/12] clk: samsung: exynos5433: Add missing clocks for CMU_FSYS domain
- [PATCH 11/12] clk: samsung: exynos5433: Add clocks for CMU_G3D domain
- [PATCH 12/12] clk: samsung: exynos5433: Add clocks for CMU_GSCL domain
This patch adds the divider/gate of CMU_GSCL domain which contains gscaler
clocks.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 ++
drivers/clk/samsung/clk-exynos5433.c | 146 ++
This patch adds the mux/divider/gate clocks for CMU_G3D domain which contains
the clocks for GPU(3D Graphics Engine).
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Reviewed-by: Pankaj Dubey
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 8 +
This patch adds the mux/divider/gate clocks for CMU_FSYS domain which
contains the clocks of USB/UFS/SDMMC/TSI/PDMA IPs.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
drivers/clk/samsung/clk-exynos5433.c | 302 +
in
This patch adds driver data for Exynos5433 SoC. Exynos5433 includes 228 multi-
functional input/output port pins and 135 memory port pins. There are 41 general
port groups and 2 memory port groups.
Cc: Tomasz Figa
Cc: Thomas Abraham
Cc: Linus Walleij
Signed-off-by: Chanwoo Choi
Acked-by: Inki
On 21 January 2015 at 11:42, Chanwoo Choi wrote:
> OK, I understand.
> I'll try to update exynos memory bus according to your comment.
Great.
@Rob: So there is nothing special required for devfreq drivers in new
OPP bindings, right ? :)
--
To unsubscribe from this list: send the line "unsubscrib
This patch adds the the mux/divider/gate clocks for CMU_DISP domain which
includes the clocks of Display IPs (DECON/HDMI/DSIM/MIXER). The CMU_DISP clocks
is used to need the source clock of CMU_MIF domain so, the CMU_MIF's clocks
related to CMU_DISP should be always on state.
Also, CMU_DISP must n
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use fin_pll source clock directly.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Reviewed-by: Pankaj Dubey
--
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and use
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
Reviewed-by: Pankaj Dubey
---
drivers/clk/samsung/clk-exynos5433.c
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
[ideal.song: Change clk flags of to pclk_gpio_* c
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A5/Bus/Audio clocks.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
Acked-by: Inki Dae
---
.../devicetree/bindings/clock/exynos5433-clock.txt | 7 +
drivers/clk/samsung/clk
This patch adds ths mux/divider/gate clocks of CMU_G2D domain which includes
G2D/MDMA IPs. The CMU_G2D must need the clocks related to G2D by providing
CMU_TOP domain. So, this patch add several clocks for G2D from CMU_TOP domain.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Cho
This patchset adds the support for Exynos5433 CMU (Clock Management Unit)
by using common clock framework. This patchset is divided from patch[1]
and then sent it.
[1] https://lkml.org/lkml/2014/12/2/134
Changelog:
Changes from v2:
- Fix the parent clock of sclk_bus_pll/sclk_mfc_pll clock on CMU_
This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.
Cc: Sylwester Nawrocki
Cc: Tomasz Figa
Signed-off-by: Chanwoo Choi
A
This patch adds the support for CMU (Clock Management Units) of Exynos5433
which is 64bit SoC and has Octa-cores. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.
Cc: Sylwester Nawrocki
Cc: Tomasz F
On 01/21/2015 01:37 PM, Viresh Kumar wrote:
> On 21 January 2015 at 09:50, Chanwoo Choi wrote:
>> If the clock will be stayed on highest voltage, will reduce
>> the considerable benefit of power-consumption.
>
> But this is exactly what you must be doing right now as well..
> I think I didn't mak
Add MAX98090 audio codec, I2S interface and the sound nodes to support
audio on Odroid-XU3 board.
Signed-off-by: Inha Song
---
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 34 ++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3.dts
On 21 January 2015 at 09:50, Chanwoo Choi wrote:
> If the clock will be stayed on highest voltage, will reduce
> the considerable benefit of power-consumption.
But this is exactly what you must be doing right now as well..
I think I didn't make it clear enough with an example. Let me
try..
This
On 01/21/2015 12:17 PM, Viresh Kumar wrote:
> On 20 January 2015 at 17:07, Chanwoo Choi wrote:
>> If each bus-block has separate regulator independently, each bus-block can
>> be registered
>> separately. But, exynos bus-blocks in mem-bus-group share the same regulator.
>
> This can be managed e
On Mon, Jan 19, 2015 at 12:21:02PM +0100, Lukasz Majewski wrote:
> After switching to device tree based configuration those declarations are
> not needed anymore.
>
> Reported-by: Abhilash Kesavan
> Signed-off-by: Lukasz Majewski
> ---
> Changes for v5:
> - New patch
> ---
> drivers/thermal/sam
On Mon, Jan 19, 2015 at 12:20:59PM +0100, Lukasz Majewski wrote:
> This patch brings support for providing configuration via device tree.
> Previously this data has been hardcoded in the exynos_tmu_data.c file.
> Such approach was not scalable and very often required copying the whole
> data.
>
>
On Mon, Jan 19, 2015 at 12:20:59PM +0100, Lukasz Majewski wrote:
> This patch brings support for providing configuration via device tree.
> Previously this data has been hardcoded in the exynos_tmu_data.c file.
> Such approach was not scalable and very often required copying the whole
> data.
>
>
On 20 January 2015 at 17:07, Chanwoo Choi wrote:
> If each bus-block has separate regulator independently, each bus-block can be
> registered
> separately. But, exynos bus-blocks in mem-bus-group share the same regulator.
This can be managed easily within the driver. Just stay the highest
voltag
Hi Kevin,
On 01/15/2015 10:08 AM, Kevin Hilman wrote:
> From: Kevin Hilman
>
> The odroid-xu3 has 4 INA231 current sensors on board which can be
> accessed from the Linux via the hwmon interface.
>
> There is one sensor for each of these power rails:
>
> - A15 cluster: VDD_ARM
> - A7 cluster:
On Mon, Jan 19, 2015 at 12:20:51PM +0100, Lukasz Majewski wrote:
> Up till now exynos_tmu_data.c was used for storing CPU cooling configuration
> data. Now the Exynos thermal core code uses device tree to get this data.
> For this purpose generic thermal code for configuring CPU cooling was
> used.
Hello Arnd,
On Mon, Jan 19, 2015 at 12:20:44PM +0100, Lukasz Majewski wrote:
> 1. Introduction
>
> Following patches aim to clean up the current implementation of the thermal
> framework on Exynos devices.
>
> The main goal was to use a generic code for reading thermal configuration
> (of-therma
On Thu, Jan 15, 2015 at 04:17:52PM +0100, Lukasz Majewski wrote:
> Hi Eduardo,
>
> > On Wed, Jan 14, 2015 at 02:41:12PM +0100, Lukasz Majewski wrote:
> > > This patch brings support for providing configuration via device
> > > tree. Previously this data has been hardcoded in the
> > > exynos_tmu_d
Hi,
On Monday 19 January 2015 18:05:07 Javier Martinez Canillas wrote:
> On 01/19/2015 05:30 PM, Thierry Reding wrote:
> >> I know you probably are very busy but it would be great if you can take a
> >> look to this series to avoid another kernel release to be missed since
> >> we are already at v
Hi,
If you want to enable the hs400 mode, need to add "mmc-hs400-1_8v" or
"mmc-hs400-1_2v".
But this patch didn't add them. do you have any other plan?
On 01/14/2015 07:30 PM, Alim Akhtar wrote:
> From: Seungwon Jeon
>
> HS400 timing values are added for SMDK5420, exynos5420-peach-pit
> and ex
Hi,
This patch can be separated.
When i tested on my board, it's not working fine.
I think it depends on my timing, so i will check after change the timing.
On 01/14/2015 07:30 PM, Alim Akhtar wrote:
> From: Seungwon Jeon
>
> Implements HS400 mode support for exynos host driver.
> This also inc
On Mon, Jan 19, 2015 at 11:44:04AM +, Lukasz Majewski wrote:
> Up till now the thermal_zone mode was by default "disabled". With this
> patch the default behavior was changed to "enable".
>
> One can read the mode at:
> /sys/class/thermal/thermal_zone0/mode
>
> Reported-by: Abhilash Kesavan
Quoting Sylwester Nawrocki (2015-01-20 06:04:00)
> Hi,
>
> On 20/01/15 11:35, Javier Martinez Canillas wrote:
> > When a power domain is powered off on Exynos5420 SoC, the input clocks of
> > the devices attached to this power domain are re-parented to oscclk and
> > restored to the original paren
Hello Lee,
On 01/20/2015 05:55 PM, Lee Jones wrote:
> On Tue, 20 Jan 2015, Javier Martinez Canillas wrote:
>
>> Hello Lee,
>>
>> On 01/20/2015 05:29 PM, Lee Jones wrote:
>> >
>> > It's not a blocker, but it is a ridiculous name to use inside the
>> > driver/ directory 'cos almost everything is
On Tue, 20 Jan 2015, Javier Martinez Canillas wrote:
> Hello Lee,
>
> On 01/20/2015 05:29 PM, Lee Jones wrote:
> >
> > It's not a blocker, but it is a ridiculous name to use inside the
> > driver/ directory 'cos almost everything is a dev(ice) here.
> >
>
> Right, do you think that "cros-ec-ch
Hello Lee,
On 01/20/2015 05:34 PM, Lee Jones wrote:
>>
>> So, the Embedded Controller driver (drivers/mfd/cros_ec.c) falls into that
>> category and in fact has been in the mfd driver for a long time. Now, if
>> an mfd device support different type of buses (e.g: i2c, spi, etc) I see
>> that both
On Tue, 20 Jan 2015, Javier Martinez Canillas wrote:
> Hello Lee,
>
> On 01/20/2015 05:36 PM, Lee Jones wrote:
> >> >
> >> > Is this safe? Are you sure it's okay to provide an interface from
> >> > userspace to read (kernel?) memory?
> >> >
> >>
> >> This interface is not to read any kernel me
Modify driver to support drm_bridge.
Signed-off-by: Ajay Kumar
Signed-off-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
---
.../devicetree/bindings/video/exynos_dp.txt| 12 +++
drivers/gpu/drm/exyno
Add drm_panel calls to the driver to make the panel and
bridge work together in tandem.
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
---
.../devicetree/bindings/drm/bridge/ptn3460
This patch does the following changes:
-- Use usleep_range instead of udelay.
-- Remove driver_private member from ptn3460 structure.
-- Make all possible functions and structures static.
-- Use dev_err for non-DRM errors.
-- Arrange header files alphabetical
Move drm/bridge documentation to video/bridge.
Also, add proper documentation for gpios used by ptn3460.
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
---
.../devicetree/bindings/d
ps8622 eDP-LVDS converter bridge chip is from parade technologies
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
---
.../devicetree/bindings/vendor-prefixes.txt|1 +
1 f
Modify driver to support gpiod interface.
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
---
drivers/gpu/drm/bridge/ptn3460.c | 88 --
1 file c
Currently, third party bridge drivers(ptn3460) are dependent
on the corresponding encoder driver init, since bridge driver
needs a drm_device pointer to finish drm initializations.
The encoder driver passes the drm_device pointer to the
bridge driver. Because of this dependency, third party drivers
Define videoports and use endpoints to describe the connection between
the encoder, bridge and the panel, instead of using phandles.
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
--
Force bridge connector detection at the end of the bridge attach.
This is needed to detect the bridge connector early.
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
---
drivers/gpu
Define videoports and use endpoints to describe the connection between
the encoder, bridge and the panel, instead of using phandles.
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
--
Assign the pointer to bridge ops structure(drm_bridge_funcs) in
the bridge driver itself, instead of passing it to drm_bridge_init.
This will allow bridge driver developer to pack bridge private
information inside the bridge object and pass only the drm-relevant
information to drm_bridge_init.
Si
This series is based on v3.19-rc5 tag of Linux-next tree at:
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
Changes since V2:
-- Address comments from Jingoo Han for ps8622 driver
-- Address comments from Daniel, Rob and Thierry regarding
bridge chaini
Use drm_bridge helpers to modify the driver to support
i2c driver model.
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
---
drivers/gpu/drm/bridge/Kconfig |2 +
drivers
Add documentation for DT properties supported by ps8622/ps8625
eDP-LVDS converter.
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tested-by: Javier Martinez Canillas
Tested-by: Gustavo Padovan
Tested-by: Sjoerd Simons
---
.../devicetree/bindings/video/bridge/ps8622.txt
From: Vincent Palatin
This patch adds drm_bridge driver for parade DisplayPort
to LVDS bridge chip.
Signed-off-by: Vincent Palatin
Signed-off-by: Andrew Bresticker
Signed-off-by: Sean Paul
Signed-off-by: Rahul Sharma
Signed-off-by: Ajay Kumar
Acked-by: Inki Dae
Tested-by: Rahul Sharma
Tes
Hello Lee,
On 01/20/2015 05:36 PM, Lee Jones wrote:
>> >
>> > Is this safe? Are you sure it's okay to provide an interface from
>> > userspace to read (kernel?) memory?
>> >
>>
>> This interface is not to read any kernel memory but only the memory mapped
>> I/O region for the Low Pin Count (LPC
On Tue, 20 Jan 2015, Javier Martinez Canillas wrote:
> Hello Lee,
>
> Thanks a lot for your feedback.
>
> On 01/20/2015 08:50 AM, Lee Jones wrote:
> >> @@ -59,9 +60,17 @@ struct cros_ec_command {
> >> *
> >> * @ec_name: name of EC device (e.g. 'chromeos-ec')
> >> * @phys_name: name of phys
Hello Lee,
On 01/20/2015 05:29 PM, Lee Jones wrote:
>
> It's not a blocker, but it is a ridiculous name to use inside the
> driver/ directory 'cos almost everything is a dev(ice) here.
>
Right, do you think that "cros-ec-chardev" will be a more suitable
name? Sorry, I'm really bad at naming thi
On Tue, 20 Jan 2015, Javier Martinez Canillas wrote:
> Hello Lee,
>
> On 01/20/2015 09:11 AM, Lee Jones wrote:
> > On Fri, 02 Jan 2015, Javier Martinez Canillas wrote:
> >
> >> From: Bill Richardson
> >>
> >> This adds the LPC interface to the Chrome OS EC. Like the
> >> I2C and SPI drivers, t
On Tue, 20 Jan 2015, Javier Martinez Canillas wrote:
> Hello Lee,
>
> Thanks a lot for your feedback.
>
> On 01/20/2015 09:20 AM, Lee Jones wrote:
> > On Fri, 02 Jan 2015, Javier Martinez Canillas wrote:
> >
> >> The ChromeOS EC character device is an user-space interface to
> >> allow applicat
Hello Lee,
Thanks a lot for your feedback.
On 01/20/2015 09:20 AM, Lee Jones wrote:
> On Fri, 02 Jan 2015, Javier Martinez Canillas wrote:
>
>> The ChromeOS EC character device is an user-space interface to
>> allow applications to access the Embedded Controller.
>>
>> Add a cell for this devic
Hello Lee,
On 01/20/2015 09:11 AM, Lee Jones wrote:
> On Fri, 02 Jan 2015, Javier Martinez Canillas wrote:
>
>> From: Bill Richardson
>>
>> This adds the LPC interface to the Chrome OS EC. Like the
>> I2C and SPI drivers, this allows userspace access to the EC.
>
> I'm fairly certain that this
On Tue, 20 Jan 2015, Krzysztof Kozlowski wrote:
> On wto, 2015-01-20 at 13:41 +, Lee Jones wrote:
> > On Mon, 05 Jan 2015, Krzysztof Kozlowski wrote:
> >
> > > Document usage of maxim,ena-gpios properties which turn on external/GPIO
> > > control over regulator.
> > >
> > > Signed-off-by: Kr
Hello Lee,
On 01/20/2015 08:48 AM, Lee Jones wrote:
>
> Looks okay to me, but I'd be happy with some more reviews from the
> Chrome guys. I would especially like some knowledgeable type to
> answer your EC_PROTO2_MAX_PARAM_SIZE question. If no one does, I
> guess it can always be changed later.
Hello Lee,
Thanks a lot for your feedback.
On 01/20/2015 08:50 AM, Lee Jones wrote:
>> @@ -59,9 +60,17 @@ struct cros_ec_command {
>> *
>> * @ec_name: name of EC device (e.g. 'chromeos-ec')
>> * @phys_name: name of physical comms layer (e.g. 'i2c-4')
>> - * @dev: Device pointer
>> + * @dev:
If system provides IOMMU feature, Exynos DRM should use it by default,
because the Exynos DRM subdrivers don't work correctly when Exynos IOMMU
driver has been enabled and no IOMMU support has been compiled into Exynos
DRM driver.
Signed-off-by: Marek Szyprowski
---
drivers/gpu/drm/exynos/Kconfi
On wto, 2015-01-20 at 13:41 +, Lee Jones wrote:
> On Mon, 05 Jan 2015, Krzysztof Kozlowski wrote:
>
> > Document usage of maxim,ena-gpios properties which turn on external/GPIO
> > control over regulator.
> >
> > Signed-off-by: Krzysztof Kozlowski
> > ---
> > Documentation/devicetree/bindin
On 15/01/15 02:50, Chanwoo Choi wrote:
> This patch adds the divider clock id for Exynos4 memory bus frequency.
> The clock id is used fo DVFS (Dynamic Voltage/Frequency Scaling)
> feature of exynos memory bus frequency.
>
> Cc: Sylwester Nawrocki
> Cc: Tomasz Figa
> Signed-off-by: Chanwoo Choi
Hello Joonyoung,
On 01/20/2015 12:12 PM, Joonyoung Shim wrote:
>>>
>>> I dug further on this issue and found that the cause is that the
>>> exynos_mixer
>>> driver needs some clocks (CLK_HDMI and CLK_SCLK_HDMI) grabbed by exynos_hdmi
>>> to be kept enabled after hdmi_poweroff
>>> (drivers/gpu/dr
Hi,
On 20/01/15 11:35, Javier Martinez Canillas wrote:
> When a power domain is powered off on Exynos5420 SoC, the input clocks of
> the devices attached to this power domain are re-parented to oscclk and
> restored to the original parent after powering on the power domain.
>
> So a reference to
On Mon, 05 Jan 2015, Krzysztof Kozlowski wrote:
> Document usage of maxim,ena-gpios properties which turn on external/GPIO
> control over regulator.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/mfd/max77686.txt | 14 ++
> 1 file changed, 14 insert
Hi Will,
On Monday 19 January 2015 11:33:31 Will Deacon wrote:
> On Mon, Jan 19, 2015 at 01:11:07AM +, Laurent Pinchart wrote:
> > On Friday 16 January 2015 10:13:11 Marek Szyprowski wrote:
> >> This patch introduces IOMMU_OF_DECLARE-based initialization to the
> >> driver, which replaces subs
Hello Marek,
On 01/20/2015 01:16 PM, Marek Szyprowski wrote:
> Mixed need to have hdmi clock enabled to properly perform power on/off
> sequences, so add handling of this clock directly to the mixer driver.
> Dependency between hdmi clock and mixer module has been observed on
> Exynos4 based board
Mixed need to have hdmi clock enabled to properly perform power on/off
sequences, so add handling of this clock directly to the mixer driver.
Dependency between hdmi clock and mixer module has been observed on
Exynos4 based boards.
Suggested-by: Andrzej Hajda
Signed-off-by: Marek Szyprowski
---
From: Andrzej Hajda
The patch adds domain definition and references to it in appropriate devices.
Signed-off-by: Andrzej Hajda
[mszyprow: rebased onto generic power domains dt bindings]
Signed-off-by: Marek Szyprowski
Tested-by: Javier Martinez Canillas
Reviewed-by: Javier Martinez Canillas
Mixed block needs to control hdmi clock to properly perform power on/off
operation, so add 'hdmi' clock also to mixer nodes.
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos5250.dtsi | 5 +++--
arch/arm/boot/dts/exynos5420.dtsi | 5 +++--
2 files changed, 6 insertions(+), 4 deletions
From: Tomasz Stanislawski
This patch adds configuration of hw modules required to enable HDMI
support on Universal C210 board.
Signed-off-by: Tomasz Stanislawski
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos4210-universal_c210.dts | 57 +
1 file changed,
This patch adds entries for HDMI, Mixer and i2c with hdmi-phy modules
found in Exynos 4210 and 4x12 SoCs.
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos4.dtsi| 40 +++
arch/arm/boot/dts/exynos4210.dtsi | 8
arch/arm/boot/dts/exynos4
This patch adds nodes specific to Exynos4412 based Odroid X/X2/U2/U3
boards required for enabling HDMI display.
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 44 +
1 file changed, 44 insertions(+)
diff --git a/arch/arm/boot/dts/exy
This patch adds support for making one power domain a sub-domain of
other domain. This is useful for modeling power dependences for devices
like TV Mixer or Camera ISP, which needs to have more than one power
domain enabled to be operational.
Based on previous work by Amit Daniel Kachhap .
Signed
TV Mixer needs both TV and LCD0 domains enabled to be fully operational.
This dependency is modelled by making TV power domains a sub-domain of
LCD0 power domain.
Signed-off-by: Marek Szyprowski
---
arch/arm/boot/dts/exynos4.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/
This patch adds a note on defining subdomains to generic PM domain
binding documentation to let power domain providers use common approach
for defining power domain hierarchy.
Signed-off-by: Marek Szyprowski
Acked-by: Geert Uytterhoeven
Reviewed-by: Ulf Hansson
---
.../devicetree/bindings/powe
Hi all,
This is yet another approach to submit patches, which enables HDMI
support for two Exynos based platforms: UniversalC210 and Odroid X2/U3.
Beside DTS changes, this patchset adds parent domain support for Exynos
PM domains. This was the most controversial patch in the previous
attempts, bu
Hello,
On 2015-01-14 17:11, Kukjin Kim wrote:
On 01/13/15 01:50, Javier Martinez Canillas wrote:
On Fri, Jan 2, 2015 at 10:36 AM, Marek Szyprowski
wrote:
This patch replaces all custom samsung,power-domain device tree properties
with generic power domain bindings and updates documentation Sam
On 01/20/2015 08:22 PM, Viresh Kumar wrote:
> On 20 January 2015 at 13:53, Chanwoo Choi wrote:
>> But, the frequency of OPPs is only used for devfreq ondemand governor.
>> After deciding the proper frequency of memory bus on ondemand governor,
>> exynos-bus.c (exynos memory bus frequency driver) u
[Adding Inki and Joonyoung to cc list]
Hello Marek,
On Mon, Jan 19, 2015 at 5:30 PM, Marek Szyprowski
wrote:
>>
>> The board instantly died then. No kernel log output from the serial
>> console, the heartbeat just stops and the board is dead. Need to
>> power-cycle to get it running again.
>>
>>
On 20 January 2015 at 13:53, Chanwoo Choi wrote:
> But, the frequency of OPPs is only used for devfreq ondemand governor.
> After deciding the proper frequency of memory bus on ondemand governor,
> exynos-bus.c (exynos memory bus frequency driver) use the frequency table
> of memory bus blocks on
On Mon, Jan 19, 2015 at 09:44:08AM +, Marc Zyngier wrote:
> IMX6 has been (ab)using the gic_arch_extn to provide
> wakeup from suspend, and it makes a lot of sense to convert
> this code to use stacked domains instead.
>
> This patch does just this, updating the DT files to actually
> reflect
On Mon, 19 Jan 2015, Mark Brown wrote:
On Mon, Jan 19, 2015 at 10:31:22AM +0100, Paul Osmialowski wrote:
On Fri, 16 Jan 2015, Mark Brown wrote:
What I'm saying is that I want to understand this change from a point of
view that isn't tied to I2C - at the regmap level what is this doing,
Hi,
On 01/14/2015 09:24 AM, Javier Martinez Canillas wrote:
> On 01/14/2015 01:19 AM, Javier Martinez Canillas wrote:
>>
>> I dug further on this issue and found that the cause is that the exynos_mixer
>> driver needs some clocks (CLK_HDMI and CLK_SCLK_HDMI) grabbed by exynos_hdmi
>> to be kept en
On Mon, Jan 19, 2015 at 10:35 PM, Javier Martinez Canillas
wrote:
> Hello Thierry,
>
> On 01/19/2015 05:30 PM, Thierry Reding wrote:
>>>
>>> I know you probably are very busy but it would be great if you can take a
>>> look
>>> to this series to avoid another kernel release to be missed since we
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the input and parent clocks for the devices attached to
a power do
The DISP1 power domain on Exynos5420 SoC includes the FIMD1, MIXER
and HDMI modules. Add a device node for this power domain and mark
these modules as consumer of the DISP1 power domain.
When a power domain is powered on and off, the input clocks of the
devices attached to it are reparented. So a
Hello,
This series adds HDMI support for Exynos5420/5422/5800 machines by adding a
node for the DISP1 power domain which is used by the HDMI and MIXER modules.
It also adds IDs for the attached devices parent and input clocks that are
used by the Exynos power domain driver to re-parent the device
Hi Pankaj,
On 2015-01-20 07:42, Pankaj Dubey wrote:
Hi Marc,
On Monday 19 January 2015 03:14 PM, Marc Zyngier wrote:
Exynos has been (ab)using the gic_arch_extn to provide
wakeup from suspend, and it makes a lot of sense to convert
this code to use stacked domains instead.
This patch does jus
On Wed, 2015-01-14 at 17:08 -0800, Kevin Hilman wrote:
> From: Kevin Hilman
>
> The odroid-xu3 has 4 INA231 current sensors on board which can be
> accessed from the Linux via the hwmon interface.
>
> There is one sensor for each of these power rails:
>
> - A15 cluster: VDD_ARM
> - A7 cluster:
Hi Viresh,
I explained the relation between memory bus group and memory bus block on
following patch[1].
- [1] https://lkml.org/lkml/2015/1/8/642
On 01/20/2015 04:19 PM, Viresh Kumar wrote:
> On 9 January 2015 at 02:48, Rob Herring wrote:
>> Adding Viresh.
>
> Sorry for being too late, I was v
On Fri, 02 Jan 2015, Javier Martinez Canillas wrote:
> The ChromeOS EC character device is an user-space interface to
> allow applications to access the Embedded Controller.
>
> Add a cell for this device so it's spawned from the mfd driver.
>
> Signed-off-by: Javier Martinez Canillas
> ---
>
Hi Tobias,
> Hello!
>
> Lukasz Majewski wrote:
> > We all know that this code is floating around - early version of
> > this work was posted in the Q3 2013.
> >
> > To be fair - this code is both needed and welcome, but new problems
> > with it are found (please search for recent comment from Ke
On Fri, 02 Jan 2015, Javier Martinez Canillas wrote:
> From: Bill Richardson
>
> This adds the LPC interface to the Chrome OS EC. Like the
> I2C and SPI drivers, this allows userspace access to the EC.
I'm fairly certain that this is _not_ an MFD device. Please locate it
to the proper subsyste
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