Many WLAN attached to a SDIO/MMC interface, needs more than one pin for
their reset sequence. For example, is very common for chips to have two
pins: one for reset and one for power enable.
This patch adds support for more reset pins to the pwrseq_simple driver
and instead hardcoding a fixed
Some WLAN chips attached to a SDIO interface, need an external clock
to be operational. Since this is very common, extend the simple MMC
power sequence DT binding to support an optional clock.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Some WLAN chips attached to a SDIO interface, need a reference clock.
Since this is very common, extend the prseq_simple driver to support
an optional clock that is enabled prior the card power up procedure.
Note, the external clock is optional. Thus an error is not returned
if the clock is not
On Tue 2015-01-27 21:13:39, Ulf Hansson wrote:
The reference counting was needed when genpd supported PM domain device
callbacks. Since this option has been removed, let's also remove the
reference counting of the struct generic_pm_domain_data.
Signed-off-by: Ulf Hansson
Many SDIO/MMC attached WLAN chips need more than one ping for their reset
sequence. Extend the pwrseq_simple binding to support more than one pin.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1:
- Make the explanation clearer by adding an explicit
Some WLAN chips attached to a SDIO interface, need a reference clock.
Since this is very common, extend the prseq_simple driver to support
an optional clock that is enabled prior the card power up procedure.
Note: the external clock is optional. Thus an error is not returned
if the clock is not
The Snow board has a MMC/SDIO wifi chip that is always powered but it
needs a power sequence involving a reset (active low) and an enable
(active high) pins. Both pins are marked as active low since the MMC
simple power sequence driver asserts the pins prior to the card power
up procedure and
On Tue 2015-01-27 21:13:38, Ulf Hansson wrote:
In a step to get consistent names of functions in genpd, rename
the internal __pm_genpd_alloc|free_dev_data() into
gendp_alloc|free_dev_data().
As discussed on the linux-pm list, let's move towards the following
name rules:
Internal
Enabling SDIO IRQ signalling for the wifi MMC/SDIO slot
doubles the transmission transfer rate.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1: None, new patch.
---
arch/arm/boot/dts/exynos5250-snow.dts | 1 +
1 file changed, 1 insertion(+)
diff
Many SDIO/MMC attached WLAN chips need more than one ping for their reset
sequence. Extend the pwrseq_simple binding to support more than one pin.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 6 +++---
1
Hello Ulf,
Many WLAN chips attached to an SDIO interface needs more than one GPIO
for their reset sequence and also an external clock to be operational.
Since this is very common, this series extend the simple MMC power sequence
to support more than one reset GPIO and also an optional external
Some WLAN chips attached to a SDIO interface, need an external clock
to be operational. Since this is very common, extend the simple MMC
power sequence DT binding to support an optional clock.
Signed-off-by: Javier Martinez Canillas javier.marti...@collabora.co.uk
---
Changes since v1: None.
---
Many WLAN attached to a SDIO/MMC interface, needs more than one pin for
their reset sequence. For example, is very common for chips to have two
pins: one for reset and one for power enable.
This patch adds support for more reset pins to the pwrseq_simple driver
and instead hardcoding a fixed
On Tue, Jan 27, 2015 at 9:13 PM, Ulf Hansson ulf.hans...@linaro.org wrote:
When __pm_genpd_add_device() is invoked through the generic OF-based PM
domain look-up path, the device is being probed. Returning an error
will mean the device won't be attached to its PM domain. Errors of
On 01/28/15 11:10, Javier Martinez Canillas wrote:
The Snow board has a MMC/SDIO wifi chip that is always powered but it
needs a power sequence involving a reset (active low) and an enable
(active high) pins. Both pins are marked as active low since the MMC
simple power sequence driver asserts
The Exynos5420 cluster power management support allowing Exynos
5420/5422/5800 machines to power up and down the secondary CPUs.
Without this option enabled, the secondary CPUs are not brought
up on boot and the following error is shown:
CPU0: thread -1, cpu 0, socket 0, mpidr 8000
Setting
On 28 January 2015 at 16:23, Tobias Jakobi liquid.a...@gmx.net wrote:
Ulf Hansson wrote:
On 28 January 2015 at 13:41, Tobias Jakobi liquid.a...@gmx.net wrote:
Hello!
Jaehoon Chung wrote:
mmc core supported to hw_reset function.
So i think we can use it. It's called at only initial time to
Ulf Hansson wrote:
On 28 January 2015 at 13:41, Tobias Jakobi liquid.a...@gmx.net wrote:
Hello!
Jaehoon Chung wrote:
mmc core supported to hw_reset function.
So i think we can use it. It's called at only initial time to clear the
previous status.
But i think it can be called at reboot
Hi,
This is for updating of mach-exynos and plat-samsung.
Please pull and if any problems, please let me know.
Thanks,
Kukjin
The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672:
Linux 3.19-rc1 (2014-12-20 17:08:50 -0800)
are available in the git repository at:
Hi Arnd, Olof, Kevin
Please pull Samsung cleanup for v3.20.
This cleanup is very nice, Samsung SoCs no more use specific DMA and
remove i2c sys from mach-exynos. Thanks to Arnd and all involved guys.
- Kukjin
The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672:
On Wednesday 28 January 2015 13:22:11 Eduardo Valentin wrote:
config ARM_EXYNOS5440_CPUFREQ
- bool SAMSUNG EXYNOS5440
+ tristate SAMSUNG EXYNOS5440
depends on SOC_EXYNOS5440
depends on HAVE_CLK OF
+ depends on THERMAL
select PM_OPP
default y
help
Hi Mike,
The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672:
Linux 3.19-rc1 (2014-12-20 17:08:50 -0800)
are available in the git repository at:
git://linuxtv.org/snawrocki/samsung.git tags/v3.20-exynos-clk
for you to fetch changes up to
Srinivas,
On 01/28/2015 05:34 PM, Srinivas Kandagatla wrote:
-- reset-gpios : contains a GPIO specifier. The reset GPIO is asserted at
-initialization and prior we start the power up procedure of the card. It
-will be de-asserted right after the power has been provided to the card.
+-
Hello Arend,
Thanks for your feedback.
On 01/28/2015 03:03 PM, Arend van Spriel wrote:
On 01/28/15 11:10, Javier Martinez Canillas wrote:
dp {
@@ -531,17 +538,33 @@
status = okay;
num-slots =1;
broken-cd;
+cap-sdio-irq;
This seems like an unrelated change, right?
Enabling thermal emulation on Exynos SoCs. New sysfs attribute - emul_temp
is created.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
arch/arm/configs/exynos_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/exynos_defconfig
Up till now, by mistake, wrong variable was tested against being NULL.
Since exynos_report_trigger() is always called with valid p pointer,
it is only necessary to check if a valid thermal zone device is passed.
Reported-by: Dan Carpenter dan.carpen...@oracle.com
Signed-off-by: Lukasz Majewski
After Exynos TMU rework to use device tree for configuration this flag
can be removed. It is not used anymore.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
arch/arm/configs/exynos_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/exynos_defconfig
These came out of running randconfig build tests on ARM. The three
patches are completely independent, so please apply what looks good.
The two s3c patches are for old bugs and should go through the
cpufreq tree.
The exynos bug only exists in the thermal-soc tree at the moment
and should get
The exynos cpufreq driver code recently gained a dependency on the
cooling code, which may be a loadable module. This breaks an ARM
allmodconfig build:
drivers/built-in.o: In function `exynos_cpufreq_probe':
:(.text+0x1748e8): undefined reference to `of_cpufreq_cooling_register'
To avoid this
The two functions s3c2416_cpufreq_driver_init and s3c_cpufreq_register
are marked init but are called from a context that might be run after
the __init sections are discarded, as the compiler points out:
WARNING: vmlinux.o(.data+0x1ad9dc): Section mismatch in reference from the
variable
Commit 32726d2d550 (ARM: SAMSUNG: Remove legacy clock code)
already removed the callback pointer, but there was one remaining
user:
drivers/cpufreq/s3c24xx-cpufreq.c: In function 's3c_cpufreq_resume_clocks':
drivers/cpufreq/s3c24xx-cpufreq.c:149:14: error: 'struct s3c_cpufreq_info' has
no member
This adds HS400 mode support for exynos dw_mmc host controller.
Currently tested on Exynos5800-peach-pi and Exyons7 platform for HS400 mode.
Tested HS200 mode with this series applied, HS200 still works.
Appreciate testing on other exynos5/7 platform which supports emmc5.0
Changes in V5:
Hi Jaehoon,
Thanks for review.
On Thu, Jan 22, 2015 at 11:28 AM, Jaehoon Chung jh80.ch...@samsung.com wrote:
Hi.
On 01/21/2015 11:12 PM, Alim Akhtar wrote:
Hi Jaehoon
On Wed, Jan 21, 2015 at 4:32 AM, Jaehoon Chung jh80.ch...@samsung.com
wrote:
Hi,
If you want to enable the hs400 mode,
Hello!
Jaehoon Chung wrote:
mmc core supported to hw_reset function.
So i think we can use it. It's called at only initial time to clear the
previous status.
But i think it can be called at reboot time. (it needs to implement codes.)
how about?
I don't think that's going the work. The
Hi Eduardo,
On Tue, Jan 27, 2015 at 11:18 AM, Abhilash Kesavan
a.kesa...@samsung.com wrote:
Add documentation for exynos7 thermal bindings including compatible
name and special clock properties.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
Hi Sylwester,
Do you have any comment about Tomasz and me reply?
Thanks,
Chanwoo Choi
On 01/24/2015 07:05 AM, Chanwoo Choi wrote:
Hi Sylwester,
On Sat, Jan 24, 2015 at 2:40 AM, Sylwester Nawrocki
s.nawro...@samsung.com wrote:
On 23/01/15 08:44, Chanwoo Choi wrote:
+ cmu_top:
From: Seungwon Jeon tgih@samsung.com
Implements HS400 mode support for exynos host driver.
This also include some updates as new mode is added.
Signed-off-by: Seungwon Jeon tgih@samsung.com
Signed-off-by: Alim Akhtar alim.akh...@samsung.com
[Alim: addressed review comments]
---
On 28 January 2015 at 18:46, Arnd Bergmann a...@arndb.de wrote:
Commit 32726d2d550 (ARM: SAMSUNG: Remove legacy clock code)
already removed the callback pointer, but there was one remaining
user:
drivers/cpufreq/s3c24xx-cpufreq.c: In function 's3c_cpufreq_resume_clocks':
From: Seungwon Jeon tgih@samsung.com
HS400 timing values are added for SMDK5420, exynos5420-peach-pit
and exynos5800-peach-pi boards.
This also adds RCLK GPIO line, this gpio should be in pull-down
state.
This also enables HS400 on peach-pi and this updates the clock frequency
to 800MHz to be
On 29 January 2015 at 01:31, Arnd Bergmann a...@arndb.de wrote:
config ARM_EXYNOS_CPUFREQ
- bool
+ tristate SAMSUNG EXYNOS CPUfreq Driver
+ depends on THERMAL
+ default y
+ help
+ This adds the CPUFreq driver for Samsung EXYNOS platforms
+
+ If in doubt,
This commit enables the cpufreq subsystem. Moreover, support for using
CPU as a cooling device is provided.
Signed-off-by: Lukasz Majewski l.majew...@samsung.com
---
arch/arm/configs/exynos_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/exynos_defconfig
Hi Javier,
You are in a lead of 3 hrs from me..
Surprisingly I send very much same patch just few Mins ago :-)
May be we can merge goods in both :-)
On 28/01/15 10:10, Javier Martinez Canillas wrote:
Many WLAN attached to a SDIO/MMC interface, needs more than one pin for
their reset sequence.
The SND_SOC_ARNDALE_RT5631_ALC5631 selects the rt5631 codec
that requires I2C to work, so we get a build error if I2C
is disabled:
codecs/rt5631.c:1737:1: warning: data definition has no type or storage class
31_i2c_driver);
codecs/rt5631.c:1737:1: error: type defaults to 'int' in declaration of
On Wed, Jan 28, 2015 at 02:16:55PM +0100, Arnd Bergmann wrote:
The exynos cpufreq driver code recently gained a dependency on the
cooling code, which may be a loadable module. This breaks an ARM
allmodconfig build:
drivers/built-in.o: In function `exynos_cpufreq_probe':
:(.text+0x1748e8):
On 28 January 2015 at 14:59, Marek Szyprowski m.szyprow...@samsung.com wrote:
There are boards (like Hardkernel's Odroid boards) on which eMMC card's
reset line is connected to GPIO line instead of the hardware reset
logic. In case of such boards, if first stage of bootloader is loaded
from
Hi Abhilash,
Add documentation for exynos7 thermal bindings including compatible
name and special clock properties.
Signed-off-by: Abhilash Kesavan a.kesa...@samsung.com
---
.../devicetree/bindings/thermal/exynos-thermal.txt |4
1 file changed, 4 insertions(+)
diff --git
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