Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check
the same before restoring the cache in resume.
This is needed for single kernel image.
Signed-off-by: Inderpal Singh inderpal.si...@linaro.org
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changes in v2:
- check processor midr instead of checking all
On Tue, Feb 26, 2013 at 03:26:53PM +0530, Inderpal Singh wrote:
Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check
the same before restoring the cache in resume.
Why is this patch soo complicated? Can't you read the CPUs MIDR register
from assembly code?
--
To
On 26 February 2013 15:32, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Feb 26, 2013 at 03:26:53PM +0530, Inderpal Singh wrote:
Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence
check
the same before restoring the cache in resume.
Why is this patch
On Tue, Feb 26, 2013 at 04:46:01PM +0530, Inderpal Singh wrote:
On 26 February 2013 15:32, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Tue, Feb 26, 2013 at 03:26:53PM +0530, Inderpal Singh wrote:
Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence
check
