On Wed, Mar 26, 2014 at 09:17:58PM +0100, Hans de Goede wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 32
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
On Wed, Mar 26, 2014 at 09:17:59PM +0100, Hans de Goede wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 59
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi
On Wed, Mar 26, 2014 at 09:18:00PM +0100, Hans de Goede wrote:
Add a new sun6i-a31-m9 dts file for the Mele M9 / Mele A1000G Quad. These
HTPCs use the same board in a different case, for more details see:
http://linux-sunxi.org/Mele_M9
Signed-off-by: Hans de Goede hdego...@redhat.com
---
Hi,
On 03/27/2014 10:44 AM, Maxime Ripard wrote:
Hi Hans,
On Wed, Mar 26, 2014 at 09:17:57PM +0100, Hans de Goede wrote:
This is necessary to support the sun6i-a31.
Signed-off-by: Hans de Goede hdego...@redhat.com
---
drivers/mmc/host/sunxi-mmc.c | 19 +++
The PMUs on sun7i use the undocumented IRQs 152 and 153 for core 0 and 1
respectively.
Signed-off-by: Mans Rullgard m...@mansr.com
---
arch/arm/plat-sunxi/devices.c | 16 +++-
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/arch/arm/plat-sunxi/devices.c
On 03/27/2014 01:00 PM, Mans Rullgard wrote:
The PMUs on sun7i use the undocumented IRQs 152 and 153 for core 0 and 1
respectively.
Are these the performance counters people where complaining about them
missing a few days ago?
How did you obtain this information? Does the one IRQ apply to
Hi,
Thanks for the patches. I've merged and pushed the 1st one.
The 2nd one esp. is a good find and a nice cleanup.
It also seems to explain why we were getting various reports about
instability on the cubieboard2, which ships with a dram clock of 480
where as it seems to be stable at 432,
Hi All,
I've rebased my u-boot sunxi-next branch on top of the
new sunxi branch which was rebased to v2014.04-rc2.
The main feature of my sunxi-next branch over the regular sunxi
branch is PSCI support, which gives users of the upstream kernel
smp + hyp mode on A20. Note that this breaks 3.4
Hi Albert,
So I've a rebased to v2014.04-rc2 tree available here:
https://github.com/jwrdegoede/u-boot-sunxi/commits/sunxi-next
Which has Maxime's initial sun6i patches, so when used with an
existing boot0 + boot1 from Allwinner this will get you
u-boot on a serial console. But it cannot load
These fixes are proposed by Hans de Goede to fix the broken kernel on
sun6i/A31. The major problem is that the IRQ number for NMI on sun6i is wrong.
Besides that, Hans proposed a fix to avoid having sporious interrupts when the
NMI line is asserted but no driver has claimed the downstream
From: Hans de Goede hdego...@redhat.com
The IRQ line used in sun6i-a31.dtsi for the NMI controller is wrong.
This causes a IRQ storm since the NMI controller is repeatedly fired.
This patch fixes this problem assigning the correct IRQ number to the
NMI controller.
Signed-off-by: Hans de Goede
Good Afternoon Doctor Hans
Updated my u-boot
I wonder how was the logic I tried to compile it like this:
./mkconfig ARCH=arm CPU=armv7 SOC=sunxi BOARD=Cubieboard2
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
No dick: (could correct me where I am going
Hi,
To build this you should do:
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- Cubieboard2_config
make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf-
Regards,
Hans
On 03/27/2014 06:33 PM, Ezaul Zillmer wrote:
Good Afternoon Doctor Hans
Updated my u-boot
I wonder how was
On Tue, 2014-03-25 at 11:00 +0100, oliver+l...@schinagl.nl wrote:
From: Olliver Schinagl oli...@schinagl.nl
This patch cleans up several macro's to remove magic values etc from
clock.c and clock.h. Casualties being dragged in are some macro's from
dram.c and the i2c driver.
This addresses
Hi,
On 03/21/2014 08:39 PM, Olliver Schinagl wrote:
David,
can you confirm/deny this change makes sense? If so, can you give mnemoc the
ok to go ahead with this fix?
Olliver
On 03/10/2014 02:58 AM, Wills Wang wrote:
---
drivers/mmc/host/sunxi-mci.h | 4 ++--
1 file changed, 2
RDIV is lacking a set of brackets compared with DIV_ROUND_UP but due to
precedence rules things work out the same for all callers.
Confirmed with objdump before and after.
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
arch/arm/cpu/armv7/sunxi/clock.c | 5 ++---
1 file changed, 2
Signed-off-by: Carlo Caione ca...@caione.org
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 40ce2df..d06ba8c 100644
Bindings documentation for the AXP20x driver. In this file also
sub-nodes are documented.
Signed-off-by: Carlo Caione ca...@caione.org
---
Documentation/devicetree/bindings/mfd/axp20x.txt | 83
1 file changed, 83 insertions(+)
create mode 100644
AXP202 and AXP209 come with two synchronous step-down DC-DCs and five
LDOs. This patch introduces basic support for those regulators.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/regulator/Kconfig| 7 +
drivers/regulator/Makefile | 1 +
Add ABI entries for the PEK found on PMU X-Powers AXP202 and AXP209.
Signed-off-by: Carlo Caione ca...@caione.org
---
Documentation/ABI/testing/sysfs-driver-input-axp-pek | 11 +++
1 file changed, 11 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-driver-input-axp-pek
AXP209 and AXP202 are the PMUs (Power Management Unit) used by A10, A13
and A20 SoCs and developed by X-Powers, a sister company of Allwinner.
AXP20x comprises an adaptive USB-Compatible PWM charger, 2 BUCK DC-DC
converters, 5 LDOs, multiple 12-bit ADCs of voltage, current and temperature
as well
This patch introduces the preliminary support for PMICs X-Powers AXP202
and AXP209. The AXP209 and AXP202 are the PMUs (Power Management Unit)
used by A10, A13 and A20 SoCs and developed by X-Powers, a sister company
of Allwinner.
The core enables support for two subsystems:
- PEK (Power Enable
This patch add support for the Power Enable Key found on MFD AXP202 and
AXP209. Besides the basic support for the button, the driver adds two
entries in sysfs to configure the time delay for power on/off.
Signed-off-by: Carlo Caione ca...@caione.org
---
drivers/input/misc/Kconfig | 11 ++
This dtsi describes the axp209 PMIC, and is to be included from inside
the i2c controller node to which the axp209 is connected.
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/x-powers-axp209.dtsi | 54
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
b/arch/arm/configs/multi_v7_defconfig
index ee69829..239c014 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 13 +
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 13 +
arch/arm/boot/dts/sun4i-a10-hackberry.dts | 19
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/configs/sunxi_defconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index b5df4a5..6e305da 100644
--- a/arch/arm/configs/sunxi_defconfig
+++
I was concerned that this would remove some barriers which were previously
implicitly present in the readl/writel calls.
Comparing the preprocessed code shows that the old code had compiler barrers
(not CPU instruction barriers) between the reads and writes while the new code
does everything as a
Picked up during upstream review.
Signed-off-by: Ian Campbell i...@hellion.org.uk
---
include/configs/sunxi-common.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h
index 7b06c99..212b621 100644
---
On Thursday, March 27, 2014 at 10:29:56 PM, Ian Campbell wrote:
On Mon, 2014-03-24 at 21:52 +0100, Marek Vasut wrote:
+static struct sunxi_timer *timer_base =
+ ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)-timer[TIMER_NUM];
+
+/* macro to read the 32 bit timer: since it
On Mon, 2014-03-24 at 22:01 +0100, Marek Vasut wrote:
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds new file mode 100644
index 000..cf02300
--- /dev/null
+++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
This file is
On Thursday, March 27, 2014 at 11:05:21 PM, Ian Campbell wrote:
On Mon, 2014-03-24 at 22:01 +0100, Marek Vasut wrote:
diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds
b/arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds new file mode 100644
index 000..cf02300
--- /dev/null
+++
On 03/27/2014 10:06 PM, Ian Campbell wrote:
On Tue, 2014-03-25 at 11:00 +0100, oliver+l...@schinagl.nl wrote:
From: Olliver Schinagl oli...@schinagl.nl
This patch cleans up several macro's to remove magic values etc from
clock.c and clock.h. Casualties being dragged in are some macro's from
On 03/27/2014 09:58 PM, Ian Campbell wrote:
On Tue, 2014-03-25 at 12:59 +0100, Olliver Schinagl wrote:
- sr32(ccm-apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
- sr32(ccm-apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
- sr32(ccm-apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);
+
Hello guys,
I want to get camera module mt9d112 working on cubieboard a10 over CSI. I
am using ubuntu linaro with kernel version 3.4.61. Test application crashes
with seg fault on (regulator_enable+0x4/0x1f8) from [bf010138]
(sensor_power+0x190/0x398 [mt9d112]). Could you please help me to
In sun5i/sun6i/sun7i, the maximum of DMA DES bits are 16, the maximum
buffer size is (1 15), so the shift bits should be
(MMC_MAX_DMA_DES_BIT - 1).
#define SDXC_DES_NUM_SHIFT(MMC_MAX_DMA_DES_BIT - 1)
#define SDXC_DES_BUFFER_MAX_LEN(1U SDXC_DES_NUM_SHIFT)
On 03/28/2014 04:40 AM, Hans
On Fri, Mar 28, 2014 at 5:29 AM, Carlo Caione ca...@caione.org wrote:
Signed-off-by: Hans de Goede hdego...@redhat.com
Signed-off-by: Carlo Caione ca...@caione.org
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 13 +
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 13
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