Hi,
On Tue, May 6, 2014 at 6:55 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, May 04, 2014 at 04:02:38PM +0200, Carlo Caione wrote:
The so called system controller in Allwinner A20 and A31 SoCs is
multi-purpose controller that tries to add misc functionality to one
memory
Hi,
On 05/05/2014 11:22 PM, hase nase wrote:
Hi,
is it possible to use an sata multiplier with a A20 ? I tried it on a
cubieboard, but i only got access to sda and no other connected drive
The sata silicon in the sunxi chips claims pmp protocol support, but
the driver disables it. I've
This patch introduces the preliminary support for PMICs X-Powers AXP202
and AXP209. The AXP209 and AXP202 are the PMUs (Power Management Unit)
used by A10, A13 and A20 SoCs and developed by X-Powers, a sister company
of Allwinner.
The core enables support for two subsystems:
- PEK
On Tuesday, May 6, 2014 8:37:53 AM UTC+2, Hans de Goede wrote:
Hi,
On 05/05/2014 11:22 PM, hase nase wrote:
Hi,
is it possible to use an sata multiplier with a A20 ? I tried it on a
cubieboard, but i only got access to sda and no other connected drive
The sata silicon in the sunxi
Hi,
On 05/06/2014 09:17 AM, mike.v...@gmail.com wrote:
On Tuesday, May 6, 2014 8:37:53 AM UTC+2, Hans de Goede wrote:
Hi,
On 05/05/2014 11:22 PM, hase nase wrote:
Hi,
is it possible to use an sata multiplier with a A20 ? I tried it on a
cubieboard, but i only got access to sda and no
On Tue, May 6, 2014 at 12:51 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sat, May 03, 2014 at 02:21:06PM +0200, Carlo Caione wrote:
On Sat, May 3, 2014 at 3:09 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
Hi,
On Thu, May 01, 2014 at 02:29:34PM +0200, Carlo
On Tue, May 6, 2014 at 8:36 AM, Chen-Yu Tsai w...@csie.org wrote:
Hi,
Hi,
On Tue, May 6, 2014 at 6:55 AM, Maxime Ripard
maxime.rip...@free-electrons.com wrote:
On Sun, May 04, 2014 at 04:02:38PM +0200, Carlo Caione wrote:
The so called system controller in Allwinner A20 and A31 SoCs is
Hi everyone,
As I mentioned in the subject, I would like to Capture from my camera, encode
it to h264 via Cedar, and stream out via RTSP.
I have downloaded, compiled and tested following two:
https://github.com/ashwing920/rtspserver
https://github.com/patrickhwood/h264encoder
rtspserver
On Sun, 4 May 2014 11:36:10 +0300
Siarhei Siamashka siarhei.siamas...@gmail.com wrote:
Hello,
Yesterday I have been trying to debug what's causing the XFCE desktop
background artefacts on my A10-Lime, which look like this:
Am Dienstag, 6. Mai 2014 10:49:55 UTC+2 schrieb Henrik Nordström:
mån 2014-05-05 klockan 14:15 -0700 skrev werr...@gmail.com:
is it possible to use an sata multiplier on a cubieboard with a A20 ?
I tried it, but i only see sda no other connected hard disk.
It is not possible.
Hi Siarhei,
Thanks for you great work (again), I had to throw out djpeg/cjpeg version check
to make it work, here's my version.
root@debian:~/cpuburn-arm# echo `djpeg -v /dev/null 21`
Independent JPEG Group's DJPEG, version 8d 15-Jan-2012 Copyright (C) 2012,
Thomas G. Lane, Guido Vollbeding
On Tue, 6 May 2014 14:24:06 +0200
Clement Wong c...@clement.hk wrote:
Hi Siarhei,
Thanks for you great work (again), I had to throw out djpeg/cjpeg version
check to make it work, here’s my version.
Thanks a lot for trying the test script on your hardware. Checking
more devices will allow
Quoting Hans de Goede (2014-05-02 08:57:14)
The first 2 patches are depenencies which should go in through the clk tree,
Mike can you pick these 2 up please ? :
Taken into clk-next.
clk: sunxi: factors: automatic reparenting support
Is uncontroversial and has been favorably reviewed by
AFAIK the SATA controller used in Allwinner chips does not support PMP due
to a
hardware limitation. That's also about the first thing about sunxi that's
written in every FAQ out there.
This FAQ is for the A10 with Sata 2.0 specs, the A20 is 2.5 specs
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Hi Mike,
On Fri, May 02, 2014 at 05:57:16PM +0200, Hans de Goede wrote:
From: Emilio López emi...@elopez.com.ar
HdG: add header exporting clk_sunxi_mmc_phase_control
Signed-off-by: Emilio López emi...@elopez.com.ar
Signed-off-by: Hans de Goede hdego...@redhat.com
Do you agree with Hans
Hi Emilio,
On Fri, May 02, 2014 at 05:57:15PM +0200, Hans de Goede wrote:
From: Emilio López emi...@elopez.com.ar
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio López emi...@elopez.com.ar
Signed-off-by: Hans de Goede
On Mon, May 05, 2014 at 08:51:13AM -0700, Guenter Roeck wrote:
On Sun, May 04, 2014 at 10:07:58PM -0500, Maxime Ripard wrote:
Hi,
This serie moves the restart code out of the mach-sunxi directory to
either the watchdog driver or to a new driver in drivers/power/reset.
Since the
I remember discussion of an MTD driver for sunxi a while back.
I can't find it in sunxi-devel, tho. Is it only available for
sunxi-3.4, or is there a branch for this MTD driver that works on newer
(DT-based) kernels?
Stefan
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Hi,
El 06/05/14 15:51, Maxime Ripard escribió:
Hi Emilio,
On Fri, May 02, 2014 at 05:57:15PM +0200, Hans de Goede wrote:
From: Emilio López emi...@elopez.com.ar
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio López
2014-05-06 21:08 GMT+04:00 Stefan Monnier monn...@iro.umontreal.ca:
I remember discussion of an MTD driver for sunxi a while back.
I can't find it in sunxi-devel, tho. Is it only available for
sunxi-3.4, or is there a branch for this MTD driver that works on newer
(DT-based) kernels?
Fix static platform_device causing module unloading to fail
Signed-off-by: Damien Nicolet zar...@gmail.com
---
drivers/w1/w1_sunxi.c | 48
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/drivers/w1/w1_sunxi.c
That code used to be in the machine code, but it's more fit here with other
restart hooks.
That will allow to cleanup the machine directory, while waiting for a proper
watchdog driver for the A31.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Acked-by: Arnd Bergmann a...@arndb.de
Hi,
This serie moves the restart code out of the mach-sunxi directory to
either the watchdog driver or to a new driver in drivers/power/reset.
Since the reset code was pretty much all the code left in the
mach-sunxi directory for all the SoCs but the A31, the only thing left
into mach-sunxi are
Now that the reset code are part of drivers of their own, we need those in the
defconfig.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig
Most of the watchdog code is duplicated between the machine restart code and
the watchdog driver. Add the restart hook to the watchdog driver, to be able to
remove it from the machine code eventually.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
Acked-by: Arnd Bergmann
The init_machine hook is now at its default value. We can remove it.
Even though the sun4i and sun7i machines are nothing more than generic machines
now, leave them in so that we won't have to add them back if needed, and so
that the machine is still displayed in /proc/cpuinfo.
Signed-off-by:
Now that the A31 reset code is a driver of its own, we need it in the
defconfig.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/configs/sunxi_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig
The A31 USB clock slightly differ from its older counterparts, mostly because
it has a different gate for each PHY, while the older one had a single gate for
all the phy.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clk/sunxi/clk-sunxi.c | 6 ++
1 file changed, 6
The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
arch/arm/boot/dts/sun6i-a31.dtsi | 77
1 file changed, 77 insertions(+)
diff --git
The OHCI controllers used in the Allwinner A31 are asserted in reset using a
global reset controller.
Add optional support for such a controller in the OHCI platform driver.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
Documentation/devicetree/bindings/usb/usb-ohci.txt | 1
From: Boris BREZILLON boris.brezil...@free-electrons.com
On the Allwinner's A31 SoC the reset line connected to the EHCI IP has to
be deasserted for the EHCI block to be usable.
Add support for an optional reset controller that will be deasserted on
power off and asserted on power on.
The USB phy controller in the A31 differs mostly from the older controllers
because it has a clock dedicated for each phy, while the older ones were having
a single clock for all the phys.
Signed-off-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/phy/phy-sun4i-usb.c | 35
Hi everyone,
This patchset adds support for the USB controllers found in the
Allwinner A31.
While the design is similar to the earlier Allwinner SoCs that are
already supported, a few details here and there change, like the fact
that the PHYs now have one clock per phy, while it used to be only
From: Boris BREZILLON boris.brezil...@free-electrons.com
The APP4 EVB1 development boards embeds an A31, together with some NAND, one SD
card slot, and one SDIO + UART WiFi and Bluetooth chip, a few I2C buses, USB,
and a LCD display.
Signed-off-by: Boris BREZILLON
Op 7 mei 2014, om 05:50 heeft Maxime Ripard maxime.rip...@free-electrons.com
het volgende geschreven:
From: Boris BREZILLON boris.brezil...@free-electrons.com
The APP4 EVB1 development boards embeds an A31, together with some NAND, one
SD
card slot, and one SDIO + UART WiFi and Bluetooth
On Tue, 6 May 2014 12:34:45 +0300
Siarhei Siamashka siarhei.siamas...@gmail.com wrote:
Implemented an automated script for running tests at different
operating points:
https://github.com/ssvb/cpuburn-arm/blob/master/cpufreq-ljt-stress-test
Only 1008MHz appears to be really problematic
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