Hello everyone! I want to run on the OV5642 sensor cubieboard2 (A20). First
tried to run OV7670. Works well. Ov5642 sensor used in another project, so the
working registers I have. Tried to use them in the driver ov5640 and get a
green screen with lower stripes, and in the background, the image
Hi,
On 06/26/2014 07:40 AM, zuobao...@gmail.com wrote:
I booting linux-3.15 on pcDuino V3(A20 onboard).
1,second CPU failed,I used https://github.com/jwrdegoede/u-boot-sunxi,then
fixed it.
2,missing clock-frequency property
Those messages can be safely ignored.
Regards,
Hans
The
Olimex has instructions up on how to build for this module...
https://www.olimex.com/wiki/A20-SOM
How to generate boot-able SD-card Debian Linux image for A20-OLinuXino?
Follow our blog post with step by step instructions Note that
Linux-Sunxi Kernel is a work-in-progress, this means you can
The PLLs on newer Allwinner SoC's, such as the A31 and A23, have a
N multiplier factor that starts from 1, not 0.
This patch adds an option to the factor clk driver's config data
structures to specify the base value of N.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard
Hi everyone,
This is v4 of the sun8i clock series, which adds basic clock
support for the A23 SoC. It is based on my initial sun8i bring
up series [1]. This series was split up from the original A23
series [2]. Yet to come are more clocks, reset controllers,
prcm, pinctrl, and mmc.
The first
The clock control unit on the A23 is similar to the one found on the A31.
The AHB1, APB1, APB2 gates on the A23 are almost identical to the ones
on the A31, but some outputs are missing.
The main CPU PLL (PLL1) however is like that on older Allwinner SoCs,
such as the A10 or A20, but the N
With sunxi_gates clocks registered with clkdev, we can use the
protected clocks list to enable the ahb_sdram clock, instead
of looking for it and adding CLK_IGNORE_UNUSED inline in the
clock setup code.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard
The new important clock protect code requires the clocks be
registered with clkdev. This was missing for sunxi_gates
type clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
Acked-by: Maxime Ripard maxime.rip...@free-electrons.com
---
drivers/clk/sunxi/clk-sunxi.c | 1 +
1 file changed, 1
A few of the clock modules have odd dividers, such as
the 2 lowest dividers being the same (2), or have the
same divider when the highest bit is set.
This patch adds support for optional divider tables,
so the clock framework will know about the odd values.
Signed-off-by: Chen-Yu Tsai
Now that we have support for sun8i specific clocks in the driver,
add the corresponding clock nodes to the DTSI. Also update the
existing peripherals with the correct clocks.
Signed-off-by: Chen-Yu Tsai w...@csie.org
---
arch/arm/boot/dts/sun8i-a23.dtsi | 125
On Wed, Jun 25, 2014 at 03:33:52PM -0700, bruce bushby wrote:
Hi Maxime
Nope... didn't think about damaging the board. I have absolutely no
idea what I'm doing :) ...it's just a hobby and I figured the only way to
learn is to try.you really don't want to watch me connecting the
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