On Tue, 21 Oct 2014 22:27:15 +0200 Maxime Ripard wrote:
> On Mon, Oct 20, 2014 at 10:33:20PM +0200, Bruno Prémont wrote:
> > Add driver for the power supply features of AXP20x PMIC.
> >
> > Covered features:
> > - backup / RTC battery
> > - VBUS/OTG power input
> > - AC power input
> > - LIon
On Sun, 29 Jun 2014 20:23:51 +0200 Carlo Caione wrote:
> During the merging of v6 several patches were left out. This v7 comprises
> all the patches that are still pending.
Any progress on this or reason why these are stuck?
> //--
>
> AXP209 and AXP202 are the PMUs (Power Management Unit) used
On Mon, Oct 20, 2014 at 10:33:20PM +0200, Bruno Prémont wrote:
> Add driver for the power supply features of AXP20x PMIC.
>
> Covered features:
> - backup / RTC battery
> - VBUS/OTG power input
> - AC power input
> - LIon battery charger
Missing Signed-off-by
> ---
> drivers/mfd/axp20x.c
Hi,
On 10/21/2014 06:21 PM, Dmitry Torokhov wrote:
Hi Hans,
On Tue, Oct 21, 2014 at 10:24:49AM +0200, Hans de Goede wrote:
+ button@98 {
+ label = "Home";
+ linux,code = ;
I do not think you really want KEY_HOM
On Mon, Oct 20, 2014 at 10:33:14PM +0200, Bruno Prémont wrote:
>
> ---
You're missing a commit log, and your signed-off-by.
You should go through Documentation/SubmittingPatches, and make sure
to run checkpatch.pl, and fix the warning and errors.
> Note: the OCV values seem to have some default
On Mon, Oct 20, 2014 at 10:10:30PM +0800, Chen-Yu Tsai wrote:
> Now that we have driver support for the basic clocks, add them to the
> dtsi and update existing peripherals. Also add reset controls to match.
>
> Signed-off-by: Chen-Yu Tsai
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electr
On Mon, Oct 20, 2014 at 10:10:28PM +0800, Chen-Yu Tsai wrote:
> This adds the gate clocks for AHB/APB busses on the A80 SoC.
>
> Signed-off-by: Chen-Yu Tsai
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
sign
On Mon, Oct 20, 2014 at 10:10:27PM +0800, Chen-Yu Tsai wrote:
> The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
> new "GT" bus, which I assume is some kind of data bus connecting
> the processor cores, memory and various busses. Also there is a
> bus clock for a ARM CCI400 module.
On Mon, Oct 20, 2014 at 10:10:26PM +0800, Chen-Yu Tsai wrote:
> Some of the factors-style clocks on the A80 have different widths
> for the mux values in the registers.
>
> Add a .muxmask field to clk_factors_config to make it configurable.
> Passing a bitmask instead of a width parameter will all
On Tue, Oct 21, 2014 at 08:03:59PM +0100, Ian Campbell wrote:
> On Sun, 2014-10-12 at 22:17 +0100, Ian Campbell wrote:
> > > -if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
> > > + default "sun4i" if TARGET_SUN4I
> > > + default "sun5i" if TARGET_SUN5I
> > > + default "sun6i" if TA
Hi Bruno,
Thanks a lot for working on this!
On Tue, Oct 21, 2014 at 06:09:16PM +0200, Bruno Prémont wrote:
> On Tue, 21 October 2014 Lee Jones wrote:
> > On Mon, 20 Oct 2014, Bruno Prémont wrote:
> > > ---
> > > Note: the OCV values seem to have some defaults build into the
> > > PMIC though may
Hi Corentin,
Thanks for resending it.
On Sun, Oct 19, 2014 at 04:16:22PM +0200, LABBE Corentin wrote:
> Add support for the Security System included in Allwinner SoC A20.
> The Security System is a hardware cryptographic accelerator that support
> AES/MD5/SHA1/DES/3DES/PRNG algorithms.
>
> Sign
On Sun, 2014-10-12 at 22:17 +0100, Ian Campbell wrote:
> > -if TARGET_SUN4I || TARGET_SUN5I || TARGET_SUN6I || TARGET_SUN7I
> > + default "sun4i" if TARGET_SUN4I
> > + default "sun5i" if TARGET_SUN5I
> > + default "sun6i" if TARGET_SUN5I
There is a typo here which is apparent with "MAKEALL -
On Fri, 2014-10-17 at 22:48 +0800, Chen-Yu Tsai wrote:
> Hi Ian,
>
> On Mon, Oct 13, 2014 at 8:57 PM, Maxime Ripard
> wrote:
> > On Sun, Oct 12, 2014 at 04:23:05PM +0800, Chen-Yu Tsai wrote:
> >> On Sun, Oct 12, 2014 at 12:05 AM, Ian Campbell wrote:
> >> > On Tue, 2014-10-07 at 15:11 +0800, Chen
On Sun, 2014-10-12 at 10:40 +0800, Chen-Yu Tsai wrote:
> On Sat, Oct 11, 2014 at 11:33 PM, Ian Campbell wrote:
> > On Sat, 2014-10-04 at 20:37 +0800, Chen-Yu Tsai wrote:
> >> +#else /* CONFIG_SUN6I || CONFIG_SUN8I || .. */
> >> + static const struct sunxi_wdog *wdog =
> >> + ((str
Hi Corentin,
On 21.10.2014 19:25, Corentin LABBE wrote:
> On 10/21/14 01:28, Vladimir Zapolskiy wrote:
>> Hello LABBE,
>>
>> On 19.10.2014 17:16, LABBE Corentin wrote:
>>> Add support for the Security System included in Allwinner SoC A20.
>>> The Security System is a hardware cryptographic acceler
Hi Hans,
Thanks, a lot for respinning this.
On Tue, Oct 21, 2014 at 10:24:47AM +0200, Hans de Goede wrote:
> Allwinnner sunxi SoCs have a low resolution adc (called lradc) which is
> specifically designed to have various (tablet) keys (ie home, back, search,
> etc). attached to it using a resisto
Le 21/10/2014 01:52, Joe Perches a écrit :
> On Tue, 2014-10-21 at 02:28 +0300, Vladimir Zapolskiy wrote:
>> On 19.10.2014 17:16, LABBE Corentin wrote:
>>> Add support for the Security System included in Allwinner SoC A20.
>>> The Security System is a hardware cryptographic accelerator that support
On 10/21/14 01:28, Vladimir Zapolskiy wrote:
> Hello LABBE,
>
> On 19.10.2014 17:16, LABBE Corentin wrote:
>> Add support for the Security System included in Allwinner SoC A20.
>> The Security System is a hardware cryptographic accelerator that support
>> AES/MD5/SHA1/DES/3DES/PRNG algorithms.
>>
Hi Hans,
On Tue, Oct 21, 2014 at 10:24:49AM +0200, Hans de Goede wrote:
> + button@98 {
> + label = "Home";
> + linux,code = ;
I do not think you really want KEY_HOME (go to the beginning of the
line) here, KEY_HOMEPAGE o
On Tue, 21 Oct 2014 08:03:57 -0700 (PDT)
Ezaul Zillmer wrote:
> results
> {"K9GBG08U0A 32G 3.3V 8-bit",
> { .id = {0xec, 0xd7, 0x94, 0x7a, 0x54, 0x43} },
> SZ_8K, SZ_4K, SZ_1M, 0, 6, 640, NAND_ECC_INFO(24, SZ_1K) },
>
>
> Start this in the attached image
> ...
I found this information more
View Picture
Em terça-feira, 21 de outubro de 2014 13h03min57s UTC-2, Ezaul Zillmer
escreveu:
>
> results
> {"K9GBG08U0A 32G 3.3V 8-bit",
> { .id = {0xec, 0xd7, 0x94, 0x7a, 0x54, 0x43} },
> SZ_8K, SZ_4K, SZ_1M, 0, 6, 640, NAND_ECC_INFO(24, SZ_1K) },
>
>
> Star
---
script_bin.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/script_bin.c b/script_bin.c
index 8da9bd7..ce13a2a 100644
--- a/script_bin.c
+++ b/script_bin.c
@@ -82,10 +82,8 @@ size_t script_bin_size(struct script *script,
}
On Tue, 21 Oct 2014 06:13:16 -0700 (PDT)
Ezaul Zillmer wrote:
> Hello everyone
>
> Boris Brezillon
>
> downloaded sunxi-nand-v6 now compiled for Cubieboard2
> https://github.com/bbrezillon/linux-sunxi.git sunxi b-nand-v6
>
> u-boot
> git clone https://github.com/jwrdegoede/u-boot-b sunxi.
On Tue, 21 Oct 2014 06:13:16 -0700 (PDT)
Ezaul Zillmer wrote:
> Hello everyone
>
> Boris Brezillon
>
> downloaded sunxi-nand-v6 now compiled for Cubieboard2
> https://github.com/bbrezillon/linux-sunxi.git sunxi b-nand-v6
>
> u-boot
> git clone https://github.com/jwrdegoede/u-boot-b sunxi.
OK vi agora V7 vou testar
Em terça-feira, 21 de outubro de 2014 11h13min16s UTC-2, Ezaul Zillmer
escreveu:
>
> Hello everyone
>
> Boris Brezillon
>
> downloaded sunxi-nand-v6 now compiled for Cubieboard2
> https://github.com/bbrezillon/linux-sunxi.git sunxi b-nand-v6
>
> u-boot
> git clone h
Hello everyone
Boris Brezillon
downloaded sunxi-nand-v6 now compiled for Cubieboard2
https://github.com/bbrezillon/linux-sunxi.git sunxi b-nand-v6
u-boot
git clone https://github.com/jwrdegoede/u-boot-b sunxi.git sunxi-wip
[1.143903] nand: Could not find valid JEDEC parameter page; abort
Hi,
This series adds support for the sunxi NAND Flash Controller (NFC)
block.
These two patches only add support for the basic NAND stuff:
- NAND controller operations
- SW and HW ECC handling (with both syndrome and normal ECC scheme)
If you want support for advanced features you can find it
Add the sunxi NAND Flash Controller dt bindings documentation.
Signed-off-by: Boris Brezillon
---
.../devicetree/bindings/mtd/sunxi-nand.txt | 45 ++
1 file changed, 45 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/sunxi-nand.txt
diff --git
Add support for the sunxi NAND Flash Controller (NFC).
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/Kconfig |6 +
drivers/mtd/nand/Makefile |1 +
drivers/mtd/nand/sunxi_nand.c | 1426 +
3 files changed, 1433 insertions(+)
create mo
Hi Brian,
On Mon, 20 Oct 2014 19:41:34 -0700
Brian Norris wrote:
> Hi Boris,
>
> On Mon, Oct 20, 2014 at 01:45:20PM +0200, Boris Brezillon wrote:
> > Add the sunxi NAND Flash Controller dt bindings documentation.
> >
> > Signed-off-by: Boris Brezillon
> > ---
> > .../devicetree/bindings/mtd/
I checked the connections... But no short connection between any four
points. I just connected X1,X2,Y1,Y2 directly to the pins of A20 board as
described. Does it need any resistor,capacitor in the connection..??? What
about sunxi-ts.c ??? Is it in proper working condition??? It is found in
so
On Mon, 20 Oct 2014, Bruno Prémont wrote:
>
> ---
> Note: the OCV values seem to have some defaults build into the
> PMIC though may need adjustment if the used battery has a different
> open circuit voltage curve.
> As far as understood (these values are set in vendor driver but not
> mentioned
This series adds a power-supply driver to cover backup/RTC battery
charger, VBUS/OTG power in, AC power in and battery charger features
supported by AXP20x PMIC.
The DT bindings documentation patch depends on the following patch
from Carlo Caione:
http://lists.infradead.org/pipermail/linux-arm-k
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 48 +
arch/arm/boot/dts/sun7i-a20.dtsi| 7
2 files changed, 55 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
b/arch/arm/boot/dts/sun7i-a2
---
arch/arm/boot/dts/sun7i-a20-cubietruck.dts |4 +
1 files changed, 2 insertions(+), 0 deletion(-)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index a6c1a3c..efb65fb 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 36
arch/arm/boot/dts/sun5i-a10s.dtsi| 7 +
arch/arm/boot/dts/sun5i-a13-olinuxino.dts| 36
arch/arm/boot/dts/sun5i-a13.dtsi
Hello LABBE,
On 19.10.2014 17:16, LABBE Corentin wrote:
> Add support for the Security System included in Allwinner SoC A20.
> The Security System is a hardware cryptographic accelerator that support
> AES/MD5/SHA1/DES/3DES/PRNG algorithms.
>
> Signed-off-by: LABBE Corentin
> ---
> drivers/cry
Hi All,
After a bit of a pause due to -ENOTIME, here is my 2nd attempt at getting
support for the lradc attached tablet keys found one some Allwinner boards
upstream.
I've dubbed this v2 even though there has been more then one version before
because I've lost count, and as said this represents t
Allwinnner sunxi SoCs have a low resolution adc (called lradc) which is
specifically designed to have various (tablet) keys (ie home, back, search,
etc). attached to it using a resistor network. This adds a driver for this.
There are 2 channels, currently this driver only supports chan0 since ther
On Tue, 2014-10-21 at 02:28 +0300, Vladimir Zapolskiy wrote:
> On 19.10.2014 17:16, LABBE Corentin wrote:
> > Add support for the Security System included in Allwinner SoC A20.
> > The Security System is a hardware cryptographic accelerator that support
> > AES/MD5/SHA1/DES/3DES/PRNG algorithms.
[
Add driver for the power supply features of AXP20x PMIC.
Covered features:
- backup / RTC battery
- VBUS/OTG power input
- AC power input
- LIon battery charger
---
drivers/mfd/axp20x.c | 106 +-
drivers/power/Kconfig|9 +
drivers/p
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun4i-a10.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 380f914..49f2200 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.d
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