> "Ian" == Ian Campbell writes:
Hi,
>> FYI, in Buildroot we currently install fexc bin2fex fex2bin bootinfo fel
>> pio for the host and nand-part for the target, all without any prefix.
> FWIW I came to the opposite conclusion wrt pio and nand-part while
> hacking
Hi,
my display is sometimes distorted after a soft reset.
(color components somehow shifted/mixed up?)
tested with kernel up to
$ uname -a
Linux green 4.2.0-1-armmp-lpae #1 SMP Debian 4.2.1-2 (2015-09-27) armv7l
GNU/Linux
Anybody else seeing this?
--
You received this message because you
On Thu, Oct 15, 2015 at 6:37 AM, Julian Calaby wrote:
> Hi Chen-Yu,
>
> On Thu, Oct 15, 2015 at 3:32 AM, Chen-Yu Tsai wrote:
>> The axp20x driver assumes the device is i2c based. This is not the
>> case with later models, which use a proprietary 2 wire
Add pinmuxing for external interrupt functionality through the
sun6i "r" pincontroller.
Signed-off-by: Hans de Goede
---
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c
The r_pio gpio / pin controller has a pin_base of non 0, we need to
adjust for this before calling sunxi_pinctrl_desc_find_function_by_pin.
Signed-off-by: Hans de Goede
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Hi Linus, Maxime,
Here are some fixes for supporting external interrupts connected to
the "r" (extra) pincontroller found on newer sunxi SoCs.
This series has been tested on a BPI-M2 which has the sdio OOB irq
hooked up to PL5, with this series applied the OOB irq works as it
should.
Regards,
When the gpio interrupt bindings where changed to add a bank to the
specifier list, the r_pio nodes of A23/A31/A33 where not updated to
match and neither was the pio node of the A80, this fixes this.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 2
On Thursday 15 October 2015 16:28:45 Hans de Goede wrote:
> When the gpio interrupt bindings where changed to add a bank to the
> specifier list, the r_pio nodes of A23/A31/A33 where not updated to
> match and neither was the pio node of the A80, this fixes this.
>
> Signed-off-by: Hans de Goede
Hi,
On 15-10-15 16:38, Arnd Bergmann wrote:
On Thursday 15 October 2015 16:28:45 Hans de Goede wrote:
When the gpio interrupt bindings where changed to add a bank to the
specifier list, the r_pio nodes of A23/A31/A33 where not updated to
match and neither was the pio node of the A80, this
Add a pinmux setting for using mmc2 in regular 4 bit mode.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/sun6i-a31.dtsi | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features
1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver,
stereo headphone jack and hdmi video output.
Signed-off-by: Hans de Goede
---
arch/arm/boot/dts/Makefile | 1
Hi,
I got Q88 tablet with a broken screen from the flea market for 4EUR.
Soldered the pins on the back for the serial port, got the console
working by powering the device from the USB port AND from the 5V DC
with a Nokia plug:
==
dram size =512
0xa215aaa5,0x410b0413
On Thu, Oct 15, 2015 at 10:27 PM, Hans de Goede wrote:
> Add pinmuxing for external interrupt functionality through the
> sun6i "r" pincontroller.
>
> Signed-off-by: Hans de Goede
Acked-by: Chen-Yu Tsai
Thanks!
--
You received this
On Thu, Oct 15, 2015 at 10:27 PM, Hans de Goede wrote:
> The r_pio gpio / pin controller has a pin_base of non 0, we need to
> adjust for this before calling sunxi_pinctrl_desc_find_function_by_pin.
>
> Signed-off-by: Hans de Goede
Acked-by: Chen-Yu
On Thu, Oct 15, 2015 at 12:32:17AM +0800, Chen-Yu Tsai wrote:
> The AXP223 is a new PMIC commonly paired with Allwinner A23/A33 SoCs.
> It is functionally identical to AXP221; only the regulator default
> voltage/status and the external host interface are different.
>
> Signed-off-by: Chen-Yu
Hi Boris,
On Fri, Oct 16, 2015 at 4:17 AM, Boris Brezillon
wrote:
> Some MLC NANDs are sensible to repeated patterns and require data to be
Do you mean "sensitive" instead of "sensible"?
Thanks,
--
Julian Calaby
Email: julian.cal...@gmail.com
Profile:
Hi Boris,
On Fri, Oct 16, 2015 at 4:17 AM, Boris Brezillon
wrote:
> Add support for the randomizer engine available in Allwinner's NFC IP.
>
> Randomization is useful to support modern NAND chips which are sensible to
Again, did you mean "sensitive" instead
The H27UCG8T2ATR-BC requires an external data scrambler. Reflect this
constraint in the nand_flash_ids definition.
Signed-off-by: Boris Brezillon
---
drivers/mtd/nand/nand_ids.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
Add support for the randomizer engine available in Allwinner's NFC IP.
Randomization is useful to support modern NAND chips which are sensible to
repeated patterns. On such NANDs you might experience an unexpectedly high
number of bitflips when you repeat the same pattern all over a given NAND
Some MLC NANDs are sensible to repeated patterns and require data to be
scrambled in order to limit the number of bitflips.
Add a new flag to let the NAND controller know about this constraint.
Signed-off-by: Boris Brezillon
---
include/linux/mtd/nand.h | 6
Hello,
This patch series aims at supporting the hardware scrambler available in
the Allwinner NAND controller, which is required to interface with some
unreliable MLC NANDs.
The main purpose of the scrambler is to avoid repeating patterns over
a specific NAND block, which can be a problem for
21 matches
Mail list logo