On 5 January 2016 at 13:05, Andre Przywara wrote:
> Hi Michal,
>
> thanks for your input!
>
> On 04/01/16 21:36, Michal Suchanek wrote:
>> Hello,
>>
>> On 4 January 2016 at 18:27, Vishnu Patekar
>> wrote:
>>> Hello Andre,
>>> This is
Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.
Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.
This patch supports the new settings, and sets them to allow non-secure
Now that we support PSCI and various security switches, we can let
U-boot boot Linux into non-secure and HYP mode.
Signed-off-by: Chen-Yu Tsai
---
board/sunxi/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index
H3 has the same power sequencing procedure as the A31/A31s, which
includes the power clamps.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/cpu/armv7/sunxi/psci_sun6i.S | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
Hi everyone,
This series enables PSCI support for the H3. Like other Allwinner SoCs,
the implementation only supports PSCI 0.1, specifically only secondary
CPU boot/hotplug.
Patch 1 supports the SMTA (previously called TZPC) TrustZone hardware
on H3. This controls non-secure access to some
H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.
Configure them to enable non-secure access.
For now the only SoC that has this feature is the H3. For other
platforms just use a default
A few weeks ago, i kinda got angry at the command line parser of
sunxi-nand-part and its inability to figure out on what kind of device
it is running. What started as a simple hack to at least make it figure
out the current partition scheme of the device became a complete rewrite.
My version
Hi Maxime,
On 04/01/16 20:30, Maxime Ripard wrote:
> Hi Andre,
>
> On Mon, Jan 04, 2016 at 10:29:06AM +, Andre Przywara wrote:
diff --git a/drivers/pinctrl/sunxi/Makefile
b/drivers/pinctrl/sunxi/Makefile
index e080290..130e7bc 100644
--- a/drivers/pinctrl/sunxi/Makefile
Hi Andre,
On Mon, Jan 04, 2016 at 11:02:37AM +, Andre Przywara wrote:
> Hi,
>
> while looking at the Allwinner A64 SoC support, I was wondering why we
> would actually need a pinctrl driver (file) for each and every Allwinner
> SoC that we support.
This was actually requested during the
Hi Michal,
thanks for your input!
On 04/01/16 21:36, Michal Suchanek wrote:
> Hello,
>
> On 4 January 2016 at 18:27, Vishnu Patekar
> wrote:
>> Hello Andre,
>> This is something we can do for future SOCs.
>>
>> On 4 Jan 2016 19:02, "Andre Przywara"
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