From: Amit Singh Tomar
Mostly by adding MACH_SUN50I to some existing #ifdefs enable support
for the the HCI0 USB host controller on the A64.
Fix up some minor 64-bit hiccups on the way.
Add the bare minimum DT bits to the A64 .dtsi and enable the controllers
and the PHY on
Hi,
these two patches enable the first USB host controller on the Pine64 board.
This allows to load and boot from USB pen drives inserted into the lower
USB socket on the board, for instance.
The first patch massages the OHCI driver to compile cleanly for 64-bit.
This is admittedly cutting some
OHCI has a known limitation of allowing only 32-bit DMA buffer
addresses, so we have a lot of u32 variables around, which are assigned
to pointers and vice versa. This obviously creates issues with 64-bit
systems, so the compiler complains here and there.
To allow compilation for 64-bit boards
On 21 October 2016 at 05:00, Maxime Ripard
wrote:
> From: Andre Przywara
>
> Signed-off-by: Andre Przywara
> Acked-by: Rob Herring
> Acked-by: Chen-Yu Tsai
> [Maxime: Change title
The sun8i-emac driver works fine with the A64 Ethernet IP, but we are
missing an alias entry to trigger the driver instantiation by U-Boot.
Add the line to point U-Boot to the Ethernet DT node.
This enables TFTP boot on the Pine64.
Signed-off-by: Andre Przywara
---
On Wed, Oct 19, 2016 at 09:40:16AM +0200, LABBE Corentin wrote:
> On Wed, Oct 05, 2016 at 12:21:30PM +0200, Jean-Francois Moine wrote:
> > On Wed, 5 Oct 2016 11:48:24 +0200
> > Corentin Labbe wrote:
> >
> > > This patch add support for the sunxi-sid driver to the
Hi,
Thank you guys for your great inputs.
Discussion was very very helpful and clarified lot of things.
Here is more of less my current master plan :)
1) finish first version of sunxi CEC adapter that is using
pooling of HDMI CEC register. This version will be without
EDID parsing. Even if we
On Tue, 18 Oct 2016, Chen-Yu Tsai wrote:
> Revert the commit for now. clocksource_mmio_init can be made to pass back
> a pointer, but the code churn and usage of an inner struct might not be
> worth it.
You can avoid the churn by making clocksurce_mmio_init() a wrapper around a
new function,
On 10/11, Maxime Ripard wrote:
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> new file mode 100644
> index ..c0e96bf6d104
> --- /dev/null
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
> +
> +static int sun50i_a64_ccu_probe(struct
I'am using a image generated with Yocto with kernel version 4.8.3 on a
A20-SOM-EVB board and keep getting this error:
Oct 20 11:05:01 olinuxino-a20 user.err kernel: [4.374646] sun7i-dwmac
1c5.ethernet: Failed to reset the dma
Oct 20 11:05:01 olinuxino-a20 user.err kernel: [4.380762]
Hi,
As it was in the first iteration, this is the A64 support based on the
new sunxi-ng clock framework.
The support for it is quite minimal at the moment, but it should be
fairly easy to add new devices, as most of the design is shared with
older SoCs.
Let me know what you think,
Maxime
From: Andre Przywara
The Pine64 is a cost-efficient development board based on the
Allwinner A64 SoC.
There are three models: the basic version with Fast Ethernet and
512 MB of DRAM (Pine64) and two Pine64+ versions, which both
feature Gigabit Ethernet and additional
From: Andre Przywara
The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
and the typical tablet / TV box peripherals.
The SoC is based on the (32-bit) Allwinner H3 chip, sharing most of
the peripherals and the memory map.
Although the cores are proper
Add the A64 CCU clocks set.
Acked-by: Rob Herring
Signed-off-by: Maxime Ripard
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +-
drivers/clk/sunxi-ng/Kconfig | 11 +-
drivers/clk/sunxi-ng/Makefile
From: Andre Przywara
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
Acked-by: Chen-Yu Tsai
[Maxime: Change title prefix to match the usual style]
Signed-off-by: Maxime Ripard
On Thu, Oct 20, 2016 at 11:14:05PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> wrote:
> > From: Andre Przywara
> >
> > The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> > and the
On Thu, Oct 20, 2016 at 11:06:21PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> wrote:
> > Allow the CCU drivers to specify a multiplier for their clocks.
> >
> > Signed-off-by: Maxime Ripard
>
On Thu, Oct 20, 2016 at 11:04:18PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> wrote:
> > Modify the current clocks we have to be able to specify the minimum for
> > each clocks we support, just like we support the max.
> >
> >
On Thu, Oct 20, 2016 at 10:35:18PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> wrote:
> > Some clocks still use an explicit list of arguments, which make it a bit
> > more tedious to add new parameters.
> >
> > Convert those
On Thu, Oct 20, 2016 at 10:30:36PM +0800, Chen-Yu Tsai wrote:
> On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
> wrote:
> > While the rational library works great, it doesn't really allow us to add
> > more constraints, like the minimum.
> >
> > Remove that in
On Thu, Oct 20, 2016 at 11:43:42AM +0800, Chen-Yu Tsai wrote:
> The A31 has 2 parallel display pipelines, which can be intermixed.
> However the driver currently only supports one of them.
>
> Signed-off-by: Chen-Yu Tsai
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
On Thu, Oct 20, 2016 at 11:43:39AM +0800, Chen-Yu Tsai wrote:
> We already have some differences between the 2 supported SoCs.
> More will be added as we support other SoCs. To avoid bloating
> the probe function with even more conditionals, move the quirks
> to a separate data structure that's
1;4402;0c
On Thu, Oct 20, 2016 at 11:43:44AM +0800, Chen-Yu Tsai wrote:
> The Hummingbird A31 board has a RGB-to-VGA bridge which converts RGB
> output from the LCD interface to VGA signals.
>
> Enable this part of the display pipeline.
>
> Signed-off-by: Chen-Yu Tsai
This one
On Thu, Oct 20, 2016 at 11:43:43AM +0800, Chen-Yu Tsai wrote:
> The LCD0 controller on the A31 can do RGB output up to 8 bits per
> channel. Add the pins for RGB888 output.
>
> Signed-off-by: Chen-Yu Tsai
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux
On Thu, Oct 20, 2016 at 11:43:41AM +0800, Chen-Yu Tsai wrote:
> The A31's display pipeline has 2 frontends, 2 backends, and 2 TCONs. It
> also has new display enhancement blocks, such as the DRC (Dynamic Range
> Controller), the DEU (Display Enhancement Unit), and the CMU (Color
> Management
On Thu, Oct 20, 2016 at 11:43:40AM +0800, Chen-Yu Tsai wrote:
> The A31 TCON has mux controls for how TCON outputs are routed to the
> HDMI and MIPI DSI blocks.
>
> Since the A31s does not have MIPI DSI, it only has a mux for the HDMI
> controller input.
>
> This patch only adds support for the
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
wrote:
> Add the A64 CCU clocks set.
>
> Acked-by: Rob Herring
> Signed-off-by: Maxime Ripard
> ---
> Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
wrote:
> From: Andre Przywara
>
> The Pine64 is a cost-efficient development board based on the
> Allwinner A64 SoC.
> There are three models: the basic version with Fast Ethernet and
> 512
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
wrote:
> From: Andre Przywara
>
> The Allwinner A64 SoC is a low-cost chip with 4 ARM Cortex-A53 cores
> and the typical tablet / TV box peripherals.
> The SoC is based on the (32-bit)
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
wrote:
> Allow the CCU drivers to specify a multiplier for their clocks.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/clk/sunxi-ng/ccu_mult.c | 2 +-
>
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
wrote:
> Modify the current clocks we have to be able to specify the minimum for
> each clocks we support, just like we support the max.
>
> Signed-off-by: Maxime Ripard
Acked-by:
Hi,
On 20-10-16 14:55, Maxime Ripard wrote:
On Thu, Oct 20, 2016 at 11:17:13AM +0200, Hans de Goede wrote:
Yes that is the idea. Although it is not really fake as theoretically
the CEC pin could be used as a general gpio. Basically the idea is that
if the hardware only offers get and set
Hi,
On 20-10-16 14:55, Maxime Ripard wrote:
On Thu, Oct 20, 2016 at 11:17:13AM +0200, Hans de Goede wrote:
Yes that is the idea. Although it is not really fake as theoretically
the CEC pin could be used as a general gpio. Basically the idea is that
if the hardware only offers get and set
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
wrote:
> Some clocks still use an explicit list of arguments, which make it a bit
> more tedious to add new parameters.
>
> Convert those over to a structure pointer argument to add as many
> arguments as possible
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
wrote:
> While the rational library works great, it doesn't really allow us to add
> more constraints, like the minimum.
>
> Remove that in order to be able to deal with the constraints we'll need.
>
>
On Tue, Oct 11, 2016 at 10:28 PM, Maxime Ripard
wrote:
> Rename the structures meant to be embedded in other structures to make it
> consistent with the mux structure name
>
> Signed-off-by: Maxime Ripard
Acked-by: Chen-Yu Tsai
On Thu, Oct 20, 2016 at 9:13 PM, Linus Walleij wrote:
> On Tue, Oct 4, 2016 at 3:51 AM, Chen-Yu Tsai wrote:
>
>> This series fixes up generic pinconf support for the sunxi pinctrl driver
>> library. The driver was doing some bits wrong, like a) storing
On Tue, Oct 4, 2016 at 3:51 AM, Chen-Yu Tsai wrote:
> This series fixes up generic pinconf support for the sunxi pinctrl driver
> library. The driver was doing some bits wrong, like a) storing the pinconf
> config value in its struct, and not actually reading the hardware to get
>
On Thu, Oct 20, 2016 at 11:43:37AM +0800, Chen-Yu Tsai wrote:
> Some rgb-to-vga bridges have an enable GPIO, either directly tied to
> an enable pin on the bridge IC, or indirectly controlling a power
> switch.
>
> Add support for it.
>
> Signed-off-by: Chen-Yu Tsai
Acked-by:
On Wed, Oct 19, 2016 at 09:02:50PM +0200, Jarosław Nieć wrote:
> On Wed, Oct 19, 2016 at 3:02 PM, Maxime Ripard <
> maxime.rip...@free-electrons.com> wrote:
>
> > Hi,
> >
> > On Mon, Oct 17, 2016 at 11:33:45PM +0200, Jarosław Nieć wrote:
> > > BTW Implementing general cec-over-gpio driver could
On 10/20/16 11:18, Hans de Goede wrote:
Hi,
On 19-10-16 21:02, Jarosław Nieć wrote:
On Wed, Oct 19, 2016 at 3:02 PM, Maxime Ripard
> wrote:
Hi,
On Mon, Oct 17, 2016 at 11:33:45PM +0200, Jarosław Nieć wrote:
Hi Hao Zhang
I am trying to develop device driver for NVP 6134 decoder chip.
It would be great help if your work is available for reference. Is it
already submitted.
Kindly let me know.
Thanks
Naveen
On Thursday, 7 July 2016 13:42:23 UTC+5:30, Hao Zhang wrote:
>
> hi all
>
> i am
Hi,
On 19-10-16 21:02, Jarosław Nieć wrote:
On Wed, Oct 19, 2016 at 3:02 PM, Maxime Ripard > wrote:
Hi,
On Mon, Oct 17, 2016 at 11:33:45PM +0200, Jarosław Nieć wrote:
> BTW Implementing general
Hi,
On 19-10-16 20:33, Jarosław Nieć wrote:
On Wed, Oct 19, 2016 at 2:55 PM, Maxime Ripard > wrote:
On Wed, Oct 19, 2016 at 11:53:10AM +0200, Hans de Goede wrote:
> > > If all the hardware allows you to-do is
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