On 02/07/17 at 08:52am, Maxime Ripard wrote:
> On Tue, Feb 07, 2017 at 05:08:16AM +0800, Icenowy Zheng wrote:
> >
> > 2017年2月7日 03:14于 Jelle van der Waa 写道:
> > >
> > > add support for the NanoPi NEO Air H3 board from friendlyarm.com . This
> > > board contains WiFi, Bluetooth, 8GB eMMC storage a
On Mon, Feb 06, 2017 at 04:56:55PM +0800, Icenowy Zheng wrote:
> 06.02.2017, 16:54, "Maxime Ripard" :
> > On Thu, Feb 02, 2017 at 09:13:37PM +0800, Icenowy Zheng wrote:
> >> The H3 SoC have a bigger SID controller, which has its direct read
> >> address at 0x200 position in the SID block, not 0x0
On Mon, Feb 06, 2017 at 10:18:14AM +, Andre Przywara wrote:
> Hi,
>
> On 03/02/17 11:14, Jagan Teki wrote:
> > On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara
> > wrote:
> >> The OrangePi PC 2 is a typical SBC with the 64-bit Allwinner H5 SoC.
> >> Create a new .dts file for it by including t
On Mon, Feb 06, 2017 at 11:29:26AM +, Andre Przywara wrote:
> Hi,
>
> On 03/02/17 10:52, Jagan Teki wrote:
> > On Wed, Feb 1, 2017 at 2:36 AM, Andre Przywara
> > wrote:
> >> Instead of enumerating all SoC families that need that bit set, let's
> >> just express this more clearly: The SMP bit
On Mon, Jan 30, 2017 at 10:02:04PM +0800, Icenowy Zheng wrote:
> > > static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = {
> > > [RST_USB_PHY0] = { 0x0cc, BIT(0) },
> > > [RST_USB_PHY1] = { 0x0cc, BIT(1) },
> > > @@ -791,6 +910,7 @@ static struct ccu_reset_map sunxi_h3_h5_ccu_resets[]
>
From: Siarhei Volkau
A31 SoC have a different map of PWM registers than others Allwinner
SoCs, so the operation of access to the registers reworked for all
existing in driver SoCs.
Tested on Onda V972 (a31) and Marsboard A20, but only PWM
channel 0, because other channels pins are not routed or
From: Siarhei Volkau
This patch introduce the sun6i PWM driver itself:
- sun6i register operations,
- sun6i prescaler table,
- DT bindings for A31 SoC,
- documentation update.
Signed-off-by: Siarhei Volkau
---
.../devicetree/bindings/pwm/pwm-sun4i.txt | 3 +-
drivers/pwm/pwm-sun4
From: Siarhei Volkau
First of all im sorry for accidentally sent old patch,
please ignore them.
This is the second version of the sun6i PWM patchset.
- added missing documentation changes
- dts changes in separate patch
Thanks to Julian Calaby for tips.
--
This series
From: Siarhei Volkau
This patch not introduce new features, just prepare code for
adding sun6i PWM driver in next commits.
A31 SoC have a different map of PWM registers than others ASoCs,
but register bits purposes are very similar.
This patch introduce set of register access routines, which
ar
From: Siarhei Volkau
This patch not introduce new features, just prepare code for
adding sun6i PWM driver in next commit.
A31 SoC have a different set of prescalers than others ASoCs, but
its position and count in the control register are the same.
This patch make the table of prescalers custom
From: Siarhei Volkau
Signed-off-by: Siarhei Volkau
---
arch/arm/boot/dts/sun6i-a31.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index ee1eb6d..fcba129 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch
Hi,
I have a board based on A20-OLinuXino-LIME2-eMMC, and I'm trying to do a
SPI communication to work(max11043), but under mainline does not work. It
works on linux sunxi-3.4, though.
Dts code:
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_a>,
<&spi1_cs0_pins_a>;
status = "oka
Hi,
I am using 4.10.0-rc5.
Also, the only spi controller driver that works on A20 is:
https://github.com/OLIMEX/OLINUXINO/blob/master/SOFTWARE/A20/A20-build-3.4.90/spi-sun7i.c
Em 8 de fev de 2017 02:07, "Icenowy Zheng" escreveu:
>
>
> 08.02.2017, 03:09, "Vinicius Maciel" :
> > Hi,
> >
> > I have
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