On Fri, May 5, 2017 at 12:52 AM, wrote:
> 在 2017-05-04 21:05,Maxime Ripard 写道:
>>
>> On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
>>>
>>> Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
>>> with mixers to do graphic processing and feed
On Thu, May 4, 2017 at 9:49 PM, Icenowy Zheng wrote:
> From: Icenowy Zheng
Do you want to update your author email address?
>
> Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
> like A20.
>
> Add support for it.
>
> Signed-off-by: Icenowy
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> Allwinner V3s SoC features a TCON without channel 1.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
--
You received this message because you are
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
> which have RGB LCD output.
Please also mention that it only has one mixer.
For the subject, you could just say "Add device nodes for the display
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> Allwinner V3s SoC features a set of pins that have functionality of RGB
> LCD, the pins are at different pin ban than other SoCs.
>
> Add pinctrl node for them.
>
> Signed-off-by: Icenowy Zheng
> ---
>
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> Allwinner V3s SoC have a display engine which have a different pipeline
> with older SoCs.
>
> Add document for it (new compatibles and the new "mixer" part).
>
> Signed-off-by: Icenowy Zheng
> Acked-by: Rob
On Thu, May 4, 2017 at 7:41 PM, Icenowy Zheng wrote:
> As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
> driver, we will finally have two types of layers.
>
> Each layer is bound to a drm_plane that is CRTC-specific, so we create
> them when initializing
On Thu, May 4, 2017 at 7:48 PM, Icenowy Zheng wrote:
> As we are going to add support for the Allwinner DE2 engine in sun4i-drm
> driver, we will finally have two types of display engines -- the DE1
> backend and the DE2 mixer. They both do some display blending and feed
>
On 05/04/2017 11:26 AM, Icenowy Zheng wrote:
>
>
> 于 2017年5月5日 GMT+08:00 上午2:21:29, Florian Fainelli 写到:
>> On 05/04/2017 11:10 AM, icen...@aosc.io wrote:
>>> 在 2017-04-22 08:22,Florian Fainelli 写道:
On 04/21/2017 04:24 PM, Icenowy Zheng wrote:
> From: Icenowy
于 2017年5月5日 GMT+08:00 上午2:21:29, Florian Fainelli 写到:
>On 05/04/2017 11:10 AM, icen...@aosc.io wrote:
>> 在 2017-04-22 08:22,Florian Fainelli 写道:
>>> On 04/21/2017 04:24 PM, Icenowy Zheng wrote:
From: Icenowy Zheng
Some RTL8211E Ethernet
On 05/04/2017 11:10 AM, icen...@aosc.io wrote:
> 在 2017-04-22 08:22,Florian Fainelli 写道:
>> On 04/21/2017 04:24 PM, Icenowy Zheng wrote:
>>> From: Icenowy Zheng
>>>
>>> Some RTL8211E Ethernet PHY have an issue that needs a workaround
>>> indicated with device tree.
>>>
>>> Add
在 2017-04-22 08:22,Florian Fainelli 写道:
On 04/21/2017 04:24 PM, Icenowy Zheng wrote:
From: Icenowy Zheng
Some RTL8211E Ethernet PHY have an issue that needs a workaround
indicated with device tree.
Add the binding for a property that indicates this workaround.
在 2017-05-05 00:57,icen...@aosc.io 写道:
在 2017-05-05 00:50,icen...@aosc.io 写道:
在 2017-05-04 21:05,Maxime Ripard 写道:
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
Allwinner have a new "Display Engine 2.0" in their new SoCs, which
comes
with mixers to do graphic processing and
Hello,
On Thu, May 04, 2017 at 02:03:14PM +0200, Maxime Ripard wrote:
> > @@ -704,6 +704,7 @@ static void pinctrl_generic_free_groups(struct
> > pinctrl_dev *pctldev)
> > radix_tree_delete(>pin_group_tree, indices[i]);
> > devm_kfree(pctldev->dev, group);
> > }
> > +
于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard
写到:
>On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
> 写到:
>> >On Thu, May 04, 2017 at 09:49:59PM +0800,
On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
> 写到:
> >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
> >> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>
On Thu, May 04, 2017 at 10:07:47PM +0800, Icenowy Zheng wrote:
>
>
> 于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard
> 写到:
> >On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
> >> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
> >>
>
On Thu, May 04, 2017 at 09:50:06PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> The Banana Pi M2 Ultra is an SBC based on the Allwinner R40 SoC. The
> form factor and position of various connectors, leds and buttons is
> similar to the Banana Pi M1+, Banana Pi M3, and is
On Thu, May 04, 2017 at 09:50:05PM +0800, Icenowy Zheng wrote:
> From: Chen-Yu Tsai
>
> The Allwinner R40 SoC is marketed as the successor to the A20 SoC.
> The R40 is a smaller chip than the A20, but features the same set
> of programmable pins, with a couple extra pins and some
于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard
写到:
>On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote:
>> Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
>>
>> Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
>>
于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard
写到:
>On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote:
>> static const struct of_device_id sun4i_a10_pinctrl_match[] = {
>> -{ .compatible = "allwinner,sun4i-a10-pinctrl", },
>> +{
>> +
Allwinner R40 has a clock controlling unit like the ones on other
Allwinner SoCs after sun6i, and can also use a CCU-based driver.
Add a compatible string for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 +
1 file changed, 1
Allwinner A10, A20 and R40 SoCs have similar GPIO layout.
Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support
into A10 driver, and add R40 support into it.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++
1 file changed, 3
As we added A20 support to A10 pinctrl driver, now we can delete the
dedicated A20 pinctrl driver, and enable A10 driver for A20.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/Kconfig |6 +-
drivers/pinctrl/sunxi/Makefile|1 -
From: Icenowy Zheng
Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals
like A20.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/arm/sunxi/README | 4
As A20 is designed as a pin-compatible upgrade of A10, their pin
controller are very similar, and can share one driver.
Add A20 support to the A10 driver.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 287 +++---
1 file
This is the first non-RFC version of this patchset, which added basical
support including I2C, UART and MMC to the mainline Linux.
The pinctrl driver of A20 is also merged into the one of A10 before
R40 support is added into the A10 driver.
Chen-Yu Tsai (2):
ARM: dts: sun8i: Add basic dtsi
On Thu, May 04, 2017 at 07:48:53PM +0800, Icenowy Zheng wrote:
> Allwinner have a new "Display Engine 2.0" in their new SoCs, which comes
> with mixers to do graphic processing and feed data to TCON, like the old
> backends and frontends.
>
> Add support for the mixer on Allwinner V3s SoC; it's
On Thu, May 04, 2017 at 07:48:47PM +0800, Icenowy Zheng wrote:
> The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
> management unit for its subunits, like the DE CCU in A80.
>
> Add a sunxi-ng style driver for it.
>
> Signed-off-by: Icenowy Zheng
> ---
>
On Thu, May 04, 2017 at 11:51:19AM +0200, Olliver Schinagl wrote:
> Hey Maxime,
>
> On 04-05-17 11:43, Maxime Ripard wrote:
> > Hi,
> >
> > On Thu, May 04, 2017 at 11:00:31AM +0200, Olliver Schinagl wrote:
> > > Sync the sun7i-a20-olinuxino-lime2-emmc.dts with the upstream kernel,
> > > which
Hi Andre,
On Thu, May 04, 2017 at 12:57:37AM +0100, Andre Przywara wrote:
> When a pinctrl driver gets interrupted during its probe process
> (returning -EPROBE_DEFER), the devres system cleans up all allocated
> resources. During this process it calls pinmux_generic_free_functions()
> and
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi.
This commit connects this panel to Lichee Pi Zero.
Lichee Pi also provides a 800x480 panel without accurate model number,
so do not merge this patch. It will finally come as device tree overlay.
Signed-off-by: Icenowy Zheng
Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON
which have RGB LCD output.
Add device nodes for it as well as the TCON.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 87
1 file changed, 87
Allwinner V3s SoC features a TCON without channel 1.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git
Allwinner V3s features the new "Display Engine 2.0", which can now also
be driven with our subdrivers in sun4i-drm.
Add the compatible string for in sun4i_drv.c, in order to make the
display engine and its components probed.
Signed-off-by: Icenowy Zheng
---
Currently the direct call from CRTC code to layer code has disappeared,
instead the layer's init function is called via the backend's ops.
Add a dedicated module for sun4i-backend and sun4i-layer, and drop the
EXPORT_SYMBOL from backend code to layer code.
Signed-off-by: Icenowy Zheng
As we are going to add support for the Allwinner DE2 engine in sun4i-drm
driver, we will finally have two types of display engines -- the DE1
backend and the DE2 mixer. They both do some display blending and feed
graphics data to TCON, so I choose to call them both "engine" here.
Abstract the
As we are going to add support for the Allwinner DE2 Mixer in sun4i-drm
driver, we will finally have two types of layers.
Each layer is bound to a drm_plane that is CRTC-specific, so we create
them when initializing CRTC (calling sun4i_layers_init, which will be
generalized in next patch). The
As sun4i-backend is now a dedicated module, add an Kconfig option for
it to make it optional, since some build may only use other engines.
Signed-off-by: Icenowy Zheng
---
Splited out patch.
drivers/gpu/drm/sun4i/Kconfig | 10 ++
drivers/gpu/drm/sun4i/Makefile | 2 +-
Allwinner V3s SoC have a display engine which have a different pipeline
with older SoCs.
Add document for it (new compatibles and the new "mixer" part).
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
Changes in v4:
- Removed the refactor at TCON
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Also add the device tree binding headers.
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
I'm sorry that some patch from this version is wrongly sent
without decorations.
This patchset is the initial patchset for Allwinner DE2 support.
It contains the support of clocks in DE2 and the mixers in DE2.
The SoC used to develop this patchset is V3s, as V3s is the simplest
one of the SoCs
The "Display Engine 2.0" in Allwinner newer SoCs contains a clock
management unit for its subunits, like the DE CCU in A80.
Add a sunxi-ng style driver for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile|
Allwinner "Display Engine 2.0" contains some clock controls in it.
In order to add them as clock drivers, we need a device tree binding.
Add the binding here.
Also add the device tree binding headers.
Signed-off-by: Icenowy Zheng
Acked-by: Rob Herring
---
From: Emmanuel Vadot
The node name for the power seq pin is mmc2@0 like the mmc2_pins_a one.
This makes the original node (mmc2_pins_a) scrapped out of the dtb and
result in a unusable eMMC if U-Boot didn't configured the pins to the
correct functions.
Signed-off-by:
This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
storage.
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC/
It is a assembly variant of the regular Lime2 but featuring eMMC for
storage.
Signed-off-by: Olliver Schinagl
---
This patch series adds support for the Olimex OLinuXino Lime2 eMMC. This
assembly variant uses eMMC flash instead of NAND (or no flash) on the other
Lime2's. Additionally, we sync the dts with upstream as we now use this dts
from the new defconfig.
Emmanuel Vadot (1):
ARM: dts: sunxi: Change
Sync the sun7i-a20-olinuxino-lime2-emmc.dts with the upstream kernel,
which fixes the power-sequencing pin being wrongfully set up.
Signed-off-by: Olliver Schinagl
---
arch/arm/dts/sun7i-a20-olinuxino-lime2-emmc.dts | 8 +++-
1 file changed, 3 insertions(+), 5
Hey ChenYu
On 04-05-17 10:48, Chen-Yu Tsai wrote:
On Thu, May 4, 2017 at 4:44 PM, Olliver Schinagl wrote:
Hey Maxime,
On 04-05-17 10:43, Maxime Ripard wrote:
On Wed, May 03, 2017 at 04:40:02PM +0200, Olliver Schinagl wrote:
This patch adds support for the Olimex
On Thu, May 4, 2017 at 4:44 PM, Olliver Schinagl wrote:
> Hey Maxime,
>
> On 04-05-17 10:43, Maxime Ripard wrote:
>>
>> On Wed, May 03, 2017 at 04:40:02PM +0200, Olliver Schinagl wrote:
>>>
>>> This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
>>> storage.
Hey Maxime,
On 04-05-17 10:43, Maxime Ripard wrote:
On Wed, May 03, 2017 at 04:40:02PM +0200, Olliver Schinagl wrote:
This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
storage.
https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC/
It is a assembly
On Wed, May 03, 2017 at 04:40:02PM +0200, Olliver Schinagl wrote:
> This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
> storage.
> https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC/
>
> It is a assembly variant of the regular Lime2 but featuring eMMC for
Hey Tim,
On 04-05-17 05:51, Tim Kryger wrote:
On Wed, May 3, 2017 at 8:40 AM, Olliver Schinagl wrote:
Hey Tim,
Ok, so as far as I understand (from the datasheet) the intended way to do
this would be to check for the BUSY IRQ & USR[0] IRQ and if it is busy,
(re-write)
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The A10s Olinuxino has an HDMI connector. Make sure we can use it.
>
> Acked-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
> ---
>
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The A10s has an HDMI controller connected to the second TCON channel. Add
> it to our DT.
>
> Since the TV Encoder was the only channel 1 user so far, also add the
> property now that we have several users.
>
On Wed, May 3, 2017 at 7:59 PM, Maxime Ripard
wrote:
> The earlier Allwinner SoCs (A10, A10s, A20, A31) have an embedded HDMI
> controller.
>
> That HDMI controller is able to do audio and CEC, but those have been left
> out for now.
>
> Signed-off-by: Maxime
On Wed, May 3, 2017 at 8:10 PM, Olliver Schinagl wrote:
> This patch adds support for the Olimex OLinuXino Lime2 with eMMC flash
> storage.
> https://www.olimex.com/Products/OLinuXino/A20/A20-OLinuXino-LIME2-eMMC/
>
> It is a assembly variant of the regular Lime2 but featuring
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