On 09/27/2017 12:34 AM, Corentin Labbe wrote:
> This patch add documentation about the MDIO switch used on sun8i-h3-emac
> for integrated PHY.
>
> Signed-off-by: Corentin Labbe
> ---
> .../devicetree/bindings/net/dwmac-sun8i.txt| 138
> +++--
On 09/27/2017 07:12 AM, Andrew Lunn wrote:
> On Wed, Sep 27, 2017 at 09:34:14AM +0200, Corentin Labbe wrote:
>> Each child node of an MDIO node is scanned as a PHY when calling
>> of_mdiobus_register() givint the following result:
>> [ 18.175379] mdio_bus stmmac-0:
The A64 is register compatible with the H3, but has a different number
of dma channels and request ports.
Attach additional properties to the node to allow future reuse of the
compatible for controllers with different number of channels/requests.
If dma-requests is not specified, the register
The current code mixes three distinct operations when transforming
the slave config to register settings:
1. special handling of DMA_SLAVE_BUSWIDTH_UNDEFINED, maxburst == 0
2. range checking
3. conversion of raw to register values
As the range checks depend on the specific SoC, move these
The spi controller nodes omit the dma controller/channel references, add
it.
This does not yet enable DMA for SPI transfers, as the spi-sun6i driver
lacks support for DMA, but always uses PIO to the FIFO.
Signed-off-by: Stefan Brüns
---
Changes in v4: None
Changes
The H3 supports bursts lengths of 1, 4, 8 and 16 transfers, each with
a width of 1, 2, 4 or 8 bytes.
The register value for the the width is log2-encoded, change the
conversion function to provide the correct value for width == 8.
Signed-off-by: Stefan Brüns
Unit-names must not start with a leading 0.
Signed-off-by: Stefan Brüns
---
Changes in v4:
- Split minor fix in devicetree example from patch 6/10
Changes in v3: None
Changes in v2: None
Documentation/devicetree/bindings/dma/sun6i-dma.txt | 2 +-
1 file
The A64 SoC has the same dma engine as the H3 (sun8i), with a
reduced amount of physical channels. To allow future reuse of the
compatible, leave the channel count etc. in the config data blank
and retrieve it from the devicetree.
Signed-off-by: Stefan Brüns
Commit 3a03ea763a67 ("dmaengine: sun6i: Add support for Allwinner A83T
(sun8i) variant") and commit f008db8c00c1 ("dmaengine: sun6i: Add support for
Allwinner H3 (sun8i) variant") added support for the A83T resp. H3, but missed
some differences between the original A31 and A83T/H3.
The first
The A64 SoC has a DMA controller that supports 8 DMA channels
to and from various peripherals. The last used DRQ port is 27.
Add a device node for it.
Signed-off-by: Stefan Brüns
---
Changes in v4: None
Changes in v3:
- Drop leading 0 from dma controller unit
For the H3, the burst lengths field offsets in the channel configuration
register differs from earlier SoC generations.
Using the A31 register macros actually configured the H3 controller
do to bursts of length 1 always, which although working leads to higher
bus utilisation.
Signed-off-by:
The H83T uses a compatible string different from the A23, but requires
the same clock autogating register setting.
The H3 also requires setting the clock autogating register, but has
the register at a different offset.
Add three suitable callbacks for the existing controller generations
and set
Preparatory patch: If the same compatible is used for different SoCs which
have a common register layout, but different number of channels, the
channel count can no longer be stored in the config. Store it in the
device structure instead.
Signed-off-by: Stefan Brüns
On Mittwoch, 27. September 2017 11:09:22 CEST Maxime Ripard wrote:
> On Sat, Sep 23, 2017 at 12:00:15AM +, Brüns, Stefan wrote:
> > On Freitag, 22. September 2017 23:30:27 CEST Maxime Ripard wrote:
> > > On Tue, Sep 19, 2017 at 04:17:59PM +, Brüns, Stefan wrote:
> > > > On Dienstag, 19.
On Wed, Sep 20, 2017 at 10:01:21PM +0200, Jernej Skrabec wrote:
> Add documentation about Allwinner DWC HDMI TX node, found in H3 SoC.
>
> Signed-off-by: Jernej Skrabec
> ---
> .../bindings/display/sunxi/sun4i-drm.txt | 158
> -
> 1 file
On Wed, Sep 27, 2017 at 09:34:14AM +0200, Corentin Labbe wrote:
> Each child node of an MDIO node is scanned as a PHY when calling
> of_mdiobus_register() givint the following result:
> [ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c3/mdio/mdio-mux has
> invalid PHY address
> [
Hi Corentin
> +Required properties for the mdio-mux node:
> + - compatible = "mdio-mux"
This is too generic. Please add a more specific compatible for this
particular mux. You can keep "mdio-mux", since that is what the MDIO
subsystem will look for.
> +Required properties of the integrated phy
On Wed, Sep 27, 2017 at 12:16:22PM +0200, Maxime Ripard wrote:
> On Wed, Sep 27, 2017 at 07:34:09AM +, Corentin Labbe wrote:
> > Since dwmac-sun8i could use either an integrated PHY or an external PHY
> > (which could be at same MDIO address), we need to represent this selection
> > by a MDIO
在 2017-09-25 18:27,Maxime Ripard 写道:
On Mon, Sep 25, 2017 at 10:12:09AM +, Icenowy Zheng wrote:
于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard
写到:
>Hi,
>
>On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote:
>> This patchset imports simple DVFS
The sunxi musb has a bug where sometimes it will generate a babble
error on device disconnect instead of a disconnect IRQ. When this
happens the musb controller switches from host mode to device mode
(it clears MUSB_DEVCTL_HM/MUSB_DEVCTL_SESSION and sets
MUSB_DEVCTL_BDEVICE) and gets stuck in this
On Wed, Sep 27, 2017 at 07:34:09AM +, Corentin Labbe wrote:
> Since dwmac-sun8i could use either an integrated PHY or an external PHY
> (which could be at same MDIO address), we need to represent this selection
> by a MDIO switch.
>
> Signed-off-by: Corentin Labbe
Hi,
On Wed, Sep 27, 2017 at 07:34:08AM +, Corentin Labbe wrote:
> This patch add documentation about the MDIO switch used on sun8i-h3-emac
> for integrated PHY.
>
> Signed-off-by: Corentin Labbe
This should be squashed with patch 1.
Maxime
--
Maxime Ripard,
On Tue, Sep 26, 2017 at 01:37:37PM +, Quentin Schulz wrote:
> On 26/09/2017 15:27, Maxime Ripard wrote:
> > On Tue, Sep 26, 2017 at 01:08:21PM +, Quentin Schulz wrote:
> >> Hi Maxime,
> >>
> >> On 26/09/2017 15:00, Maxime Ripard wrote:
> >>> On Tue, Sep 26, 2017 at 12:17:12PM +,
On Sat, Sep 23, 2017 at 12:00:15AM +, Brüns, Stefan wrote:
> On Freitag, 22. September 2017 23:30:27 CEST Maxime Ripard wrote:
> > On Tue, Sep 19, 2017 at 04:17:59PM +, Brüns, Stefan wrote:
> > > On Dienstag, 19. September 2017 16:25:08 CEST Maxime Ripard wrote:
> > > > On Mon, Sep 18,
Each child node of an MDIO node is scanned as a PHY when calling
of_mdiobus_register() givint the following result:
[ 18.175379] mdio_bus stmmac-0: /soc/ethernet@1c3/mdio/mdio-mux has
invalid PHY address
[ 18.175408] mdio_bus stmmac-0: scan phy mdio-mux at address 0
[ 18.175450]
This patch restore dt-bindings documentation about dwmac-sun8i
This reverts commit 8aa33ec2f481 ("dt-bindings: net: Revert sun8i dwmac
binding")
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 84 ++
1 file
Hello
The current way to find if the PHY is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the integrated one.
This patchs series adds a new way to find if the PHY is integrated, via
the
The current way to find if the phy is internal is to compare DT phy-mode
and emac_variant/internal_phy.
But it will negate a possible future SoC where an external PHY use the
same phy mode than the internal one.
This patch adds a new way to find if the PHY is internal, via
the phy-is-integrated
The Allwinner H3 SoC have two distinct MDIO bus, only one could be
active at the same time.
The selection of the active MDIO bus are done via some bits in the EMAC
register of the system controller.
This patch implement this MDIO switch via a custom MDIO-mux.
Signed-off-by: Corentin Labbe
Since dwmac-sun8i could use either an integrated PHY or an external PHY
(which could be at same MDIO address), we need to represent this selection
by a MDIO switch.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 31
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Signed-off-by: Corentin Labbe
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi |
stmmac bindings docs said that its mdio node must have
compatible = "snps,dwmac-mdio";
Since dwmac-sun8i does not have any good reasons to not doing it, all
their MDIO node must have it.
Since these compatible is automatically registered, dwmac-sun8i compatible
does not need to be in
This patch restore arm DT about dwmac-sun8i
This reverts commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9
arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts |
This patch add documentation about the MDIO switch used on sun8i-h3-emac
for integrated PHY.
Signed-off-by: Corentin Labbe
---
.../devicetree/bindings/net/dwmac-sun8i.txt| 138 +++--
1 file changed, 126 insertions(+), 12 deletions(-)
diff
This patch restore arm64 DT about dwmac-sun8i
This reverts commit 87e1f5e8bb4b ("arm64: dts: allwinner: Revert EMAC changes")
Signed-off-by: Corentin Labbe
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 16
This patch restore compatibles about dwmac-sun8i
This reverts commit ad4540cc5aa3 ("net: stmmac: sun8i: Remove the compatibles")
Signed-off-by: Corentin Labbe
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8
1 file changed, 8 insertions(+)
diff
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