On Tue, Oct 17, 2017 at 12:23 PM, Chen-Yu Tsai wrote:
> Hi,
>
> Here's another bunch of cleanups for sun4i-drm. Most of these were
> found while working on A10/A20 DRM and HDMI support. To be clear,
> nothing was broken before these patches.
>
> Changes since v1:
>
> - Expanded commit message fo
Many of the backend's layer configuration registers have undefined
default values. This poses a risk as we use regmap_update_bits in
some places, and don't overwrite the whole register.
At probe/bind time we explicitly clear all the control registers
by writing 0 to them. This patch adds a more de
Initially we configured the PAD_CTRL1 register at probe/bind time.
However it seems the HDMI controller will modify some of the bits
in this register by itself. On the A10 it is particularly annoying
as it toggles the output invert bits, which inverts the colors on
the display output.
The U-boot d
The backend has various clocks and reset controls that need to be
enabled and deasserted before register access is possible.
Move the creation of the regmap to after the clocks and reset controls
have been configured where it makes more sense.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun
Commit 4636ce93d5b2 ("drm/fb-cma-helper: Add drm_fb_cma_get_gem_addr()")
adds a new helper, which covers fetching a drm_framebuffer's GEM object
and calculating the buffer address for a given plane.
This patch uses this helper to replace our own open coded version of the
same function.
Signed-off
The display backend, as well as other peripherals that have a DRAM
clock gate and access DRAM directly, bypassing the system bus,
address the DRAM starting from 0x0, while physical addresses the
system uses starts from 0x4000 (or 0x2000 in A80's case).
This issue was witnessed on the Cubie
Even though the components framework can handle duplicate entries,
the extra entries cause a lot more debug messages to be generated,
which would be confusing to developers not familiar with our driver
and the framework in general.
Instead, we can scan the relatively small queue and check if the
c
Hi,
Here's another bunch of cleanups for sun4i-drm. Most of these were
found while working on A10/A20 DRM and HDMI support. To be clear,
nothing was broken before these patches.
Changes since v1:
- Expanded commit message for patch 5 explaining the details of
memory address difference, wra
While debugging inverted color from the HDMI output on the A10, I
found that the lowest 3 bits were set. These were cleared on A20
boards that had normal display output. By manually toggling these
bits the mapping of the color components to these bits was found.
While these are not used anywhere,
On Mon, Oct 16, 2017 at 11:54:27PM +1100, Jonathan Liu wrote:
> On 16 October 2017 at 23:49, Bin Liu wrote:
> > On Mon, Oct 16, 2017 at 04:13:51PM +1100, Jonathan Liu wrote:
> >> On 10 October 2017 at 14:22, Bin Liu wrote:
> >> > On Tue, Oct 10, 2017 at 01:45:25PM +1100, Jonathan Liu wrote:
> >>
On Tue, Oct 17, 2017 at 4:15 AM, Maxime Ripard
wrote:
> On Mon, Oct 16, 2017 at 04:20:32PM +0800, Chen-Yu Tsai wrote:
>> > On Sat, Oct 14, 2017 at 12:02:50PM +0800, Chen-Yu Tsai wrote:
>> >> The display backend, as well as other peripherals that have a DRAM
>> >> clock gate and access DRAM directl
To avoid introduction of a new compatible for each small SoC/DMA controller
variation, move the definition of the channel count to the devicetree.
The number of vchans is no longer explicit, but limited by the highest
port/DMA request number. The result is a slight overallocation for SoCs
with a s
On Mon, Oct 16, 2017 at 04:20:32PM +0800, Chen-Yu Tsai wrote:
> > On Sat, Oct 14, 2017 at 12:02:50PM +0800, Chen-Yu Tsai wrote:
> >> The display backend, as well as other peripherals that have a DRAM
> >> clock gate and access DRAM directly, bypassing the system bus,
> >> address the DRAM starting
On Mon, Oct 16, 2017 at 02:21:02PM +, Brüns, Stefan wrote:
> On Montag, 16. Oktober 2017 09:02:17 CEST Vinod Koul wrote:
> > On Thu, Sep 28, 2017 at 03:49:24AM +0200, Stefan Brüns wrote:
> > > To avoid introduction of a new compatible for each small SoC/DMA
> > > controller
> > > variation, mov
Hello Yong,
Did you test CPU load during capture frames from CSI and now many fps did
you get?
Recently i noticed problem with CPU load which is related to fps not to
resolution on old 3.4.75 kernel on A20 platform.
I opened new topic few weeks ago but i did not get any answer yet..
Maybe you c
On Montag, 16. Oktober 2017 09:02:17 CEST Vinod Koul wrote:
> On Thu, Sep 28, 2017 at 03:49:24AM +0200, Stefan Brüns wrote:
> > To avoid introduction of a new compatible for each small SoC/DMA
> > controller
> > variation, move the definition of the channel count to the devicetree.
> >
> > The num
Hi,
First, i have never used LiveSuit, i use PhoenixSuit..
Packing/Unpacking image for phoenixsuit have to be done with with
imgRePacker tool.
Link: https://forum.xda-developers.com/showthread.php?t=1753473
My advice is to find already ready image which work with phoenixsuite for
cubieboard2 a
icen...@aosc.io writes:
> > > Like I asked already last time, AFAICS there is no upstream xr819
> > > wireless driver in drivers/net/wireless directory. Do we still
accept
> > > bindings like this for out-of-tree drivers?
> >
> > See esp8089.
> >
> > There's also n
On 16 October 2017 at 23:49, Bin Liu wrote:
> On Mon, Oct 16, 2017 at 04:13:51PM +1100, Jonathan Liu wrote:
>> On 10 October 2017 at 14:22, Bin Liu wrote:
>> > On Tue, Oct 10, 2017 at 01:45:25PM +1100, Jonathan Liu wrote:
>> >> This fixes a kernel oops when unloading the driver due to usb_put_phy
On Mon, Oct 16, 2017 at 04:13:51PM +1100, Jonathan Liu wrote:
> On 10 October 2017 at 14:22, Bin Liu wrote:
> > On Tue, Oct 10, 2017 at 01:45:25PM +1100, Jonathan Liu wrote:
> >> This fixes a kernel oops when unloading the driver due to usb_put_phy
> >> being called after usb_phy_generic_unregiste
On Mon, Oct 16, 2017 at 05:41:10PM +0800, icen...@aosc.io wrote:
> 在 2017-10-16 17:11，Maxime Ripard 写道：
> > On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> > > A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be
> > > claimed.
> >
> > Why?
>
> Allwinner didn't documen
On Mon, Oct 16, 2017 at 05:39:58PM +0800, icen...@aosc.io wrote:
> 在 2017-10-16 17:32，Maxime Ripard 写道：
> > On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote:
> > > >> + interrupts = ;
> > > >> + clocks = <&ccu CLK_BUS_OHCI1>,
> > > >> +
在 2017-10-16 16:00，Maxime Ripard 写道：
Hi,
I've applied all the other patches.
On Sat, Oct 14, 2017 at 12:02:50PM +0800, Chen-Yu Tsai wrote:
The display backend, as well as other peripherals that have a DRAM
clock gate and access DRAM directly, bypassing the system bus,
address the DRAM starting
在 2017-10-16 17:11，Maxime Ripard 写道：
On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be
claimed.
Why?
Allwinner didn't document this, but if the SRAM is not claimed, the
DE2 MMIO zone is totally not accessible.
It s
在 2017-10-16 17:32，Maxime Ripard 写道：
On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote:
>> + interrupts = ;
>> + clocks = <&ccu CLK_BUS_OHCI1>,
>> + <&ccu CLK_BUS_EHCI1>,
>> + <&ccu
On Tue, Oct 10, 2017 at 07:24:28AM +0800, Icenowy Zheng wrote:
> >> + interrupts = ;
> >> + clocks = <&ccu CLK_BUS_OHCI1>,
> >> + <&ccu CLK_BUS_EHCI1>,
> >> + <&ccu CLK_USB_OHCI1>;
> >> + resets =
On Sat, Oct 14, 2017 at 08:29:24PM +0800, Icenowy Zheng wrote:
> A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed.
Why?
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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You received this message because you are subscribe
On Fri, Oct 13, 2017 at 07:26:21PM +0800, Icenowy Zheng wrote:
> The R40 SoC has a watchdog like the one on A20, in the timer memory zone
> (which is also the same on A20).
>
> Add the device tree node for it.
>
> Signed-off-by: Icenowy Zheng
Applied, thanks!
Maxime
--
Maxime Ripard, Free Ele
Hi,
On Mon, Oct 16, 2017 at 4:00 PM, Maxime Ripard
wrote:
> Hi,
>
> I've applied all the other patches.
>
> On Sat, Oct 14, 2017 at 12:02:50PM +0800, Chen-Yu Tsai wrote:
>> The display backend, as well as other peripherals that have a DRAM
>> clock gate and access DRAM directly, bypassing the sys
Hi,
I've applied all the other patches.
On Sat, Oct 14, 2017 at 12:02:50PM +0800, Chen-Yu Tsai wrote:
> The display backend, as well as other peripherals that have a DRAM
> clock gate and access DRAM directly, bypassing the system bus,
> address the DRAM starting from 0x0, while physical addresse
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