On Thu, Dec 21, 2017 at 8:55 AM, Maxime Ripard
wrote:
> Hi Kyle,
>
> On Tue, Dec 19, 2017 at 03:05:23PM -0600, kevan...@ksu.edu wrote:
>> Allwinner a83t has a 1 KB sid block with efuse for security rootkey and
>> thermal calibration data, add node to describe it.
On Thu, Dec 21, 2017 at 9:26 AM, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Dec 21, 2017 at 09:19:24AM -0600, Kyle Evans wrote:
>> On Thu, Dec 21, 2017 at 8:55 AM, Maxime Ripard
>> wrote:
>> > Hi Kyle,
>> >
>> > On Tue, Dec 19, 2017
On Thu, Dec 21, 2017 at 11:26 PM, Maxime Ripard
wrote:
> Hi,
>
> On Thu, Dec 21, 2017 at 09:19:24AM -0600, Kyle Evans wrote:
>> On Thu, Dec 21, 2017 at 8:55 AM, Maxime Ripard
>> wrote:
>> > Hi Kyle,
>> >
>> > On Tue, Dec 19,
Hi,
On Thu, Dec 21, 2017 at 09:19:24AM -0600, Kyle Evans wrote:
> On Thu, Dec 21, 2017 at 8:55 AM, Maxime Ripard
> wrote:
> > Hi Kyle,
> >
> > On Tue, Dec 19, 2017 at 03:05:23PM -0600, kevan...@ksu.edu wrote:
> >> Allwinner a83t has a 1 KB sid block with efuse
On Thu, Dec 21, 2017 at 11:05:36PM +0800, Icenowy Zheng wrote:
> The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
> controllers.
>
> Add the device nodes for the controllers.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 19
On Thu, Dec 21, 2017 at 11:05:35PM +0800, Icenowy Zheng wrote:
> As the PHY dual-route property is added to 4.15-rc, the EHCI/OHCI nodes
> are now necessary.
>
> Please apply these patches to 4.15, Thanks!
There's no reason to have it merged in 4.15. It's not a regression,
so 4.15 should work
Hi,
On Thu, Dec 21, 2017 at 11:05:36PM +0800, Icenowy Zheng wrote:
> The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
> controllers.
>
> Add the device nodes for the controllers.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 19
As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8
1 file changed, 8 insertions(+)
diff --git
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git
As the PHY dual-route property is added to 4.15-rc, the EHCI/OHCI nodes
are now necessary.
Please apply these patches to 4.15, Thanks!
Icenowy Zheng (2):
ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
Hi Kyle,
On Tue, Dec 19, 2017 at 03:05:23PM -0600, kevan...@ksu.edu wrote:
> Allwinner a83t has a 1 KB sid block with efuse for security rootkey and
> thermal calibration data, add node to describe it.
>
> a83t-sid is not currently supported by nvmem/sunxi-sid, but it is
> supported in an
Hi,
On Thu, Dec 21, 2017 at 10:24:11PM +1100, Jonathan Liu wrote:
> There are several issues in sun4i_tmds_determine_rate:
> - doesn't check if the best match was already set before comparing it
> with the enumerated parameters which could result in integer divide
> by zero
> - doesn't
There are several issues in sun4i_tmds_determine_rate:
- doesn't check if the best match was already set before comparing it
with the enumerated parameters which could result in integer divide
by zero
- doesn't consider rate halving when determining closest match if it
can't match the
Hello Petar,
Can you point me where i can order same V3s based board?
BR,
Siarhei
--
You received this message because you are subscribed to the Google Groups
"linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email
to
14 matches
Mail list logo