Hi.
Thanks for the sample code.
I read the register (Attached file with comments) and compared them with the
Allwinner User Manual V1.1
Summary Clock:
Video0 = 24MHz*99/8=297MHz
MIPI based on Video0 = 297MHz*3*2/5=356,4MHz
Then the pixel clock is 356,4MHz/7=50,914MHz
Requested is 51,45MHz
-->
Hi Maxime,
On Tue, May 21, 2019 at 01:46:11PM +0200, Maxime Ripard wrote:
> Hi,
>
> On Tue, May 21, 2019 at 01:50:08AM +0200, meg...@megous.com wrote:
> > From: Ondrej Jirman
> >
> > Orange Pi 3 board requires enabling a voltage shifting circuit via GPIO
> > for the DDC bus to be usable.
> >
>
Hi,
On Tue, May 21, 2019 at 01:50:08AM +0200, meg...@megous.com wrote:
> From: Ondrej Jirman
>
> Orange Pi 3 board requires enabling a voltage shifting circuit via GPIO
> for the DDC bus to be usable.
>
> Add support for hdmi-connector node's optional ddc-en-gpios property to
> support this use
Hi Maxime
On Tue, May 21, 2019 at 10:10 AM Maxime Ripard
wrote:
>
> On Tue, May 21, 2019 at 08:47:02AM +0200, Michael Nazzareno Trimarchi wrote:
> > > > + };
> > > > +
> > > > };
> > > >
> > > > {
> > > > @@ -77,6 +95,31 @@
> > > > status = "okay";
> > > > };
> > > >
> > > > + {
>
Hello Sergei,
On Tue, May 21, 2019 at 12:27:24PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 21.05.2019 2:50, meg...@megous.com wrote:
>
> > From: Icenowy Zheng
> >
> > The PHY selection bit also exists on SoCs without an internal PHY; if it's
> > set to 1 (internal PHY, default value) then
Hello!
On 21.05.2019 2:50, meg...@megous.com wrote:
From: Icenowy Zheng
The PHY selection bit also exists on SoCs without an internal PHY; if it's
set to 1 (internal PHY, default value) then the MAC will not make use of
any PHY such SoCs.
^ "on" or "with" missing?
This problem
On Tue, May 21, 2019 at 07:24:32AM +, Kamps, John-Eric wrote:
> Hi Jagan
>
> >Possible checks.
>
> >01. Try the bsp first, since we don't have any kind of reference documents.
> OK I will compare them
>
> >02: Identify the working pixel clock rates along with dividers
> I will check the
On Tue, May 21, 2019 at 08:47:02AM +0200, Michael Nazzareno Trimarchi wrote:
> > > + };
> > > +
> > > };
> > >
> > > {
> > > @@ -77,6 +95,31 @@
> > > status = "okay";
> > > };
> > >
> > > + {
> > > + can_pins: can-pins {
> > > + pins = "PD6", /*
Hi Jagan
>Possible checks.
>01. Try the bsp first, since we don't have any kind of reference documents.
OK I will compare them
>02: Identify the working pixel clock rates along with dividers
I will check the kernel log from the original device.
>03: Better get the regmap of tcon0 and other
Hi Maxime
On Thu, Apr 18, 2019 at 4:56 PM Maxime Ripard wrote:
>
> On Thu, Apr 18, 2019 at 07:46:58PM +0530, Jagan Teki wrote:
> > Oceanic 5205 5inMFD has MCP2515 CAN device connected via SPI1.
> >
> > - via SPI1 bus
> > - vdd supplied by 5V supply along with PL2 enable pin
> > - xceiver supply
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