I built a spreadsheet and worked out all of the possible divider
combinations for the audio PLL2.
These two from the Allwinner code are the only two useful combinations.
/* FactorN=79, PreDiv=21, PostDiv=4,
output=24*79/21/4=22.571mhz, 44.1k series fs
FactorN=86,
Hi,
On Sun, Jun 15, 2014 at 10:56 PM, jonsm...@gmail.com jonsm...@gmail.com wrote:
I built a spreadsheet and worked out all of the possible divider
combinations for the audio PLL2.
These two from the Allwinner code are the only two useful combinations.
/* FactorN=79, PreDiv=21,
What should the clocks be?
Why are there three I2S devices?
Did I get interrupt and DMA values right?
spdif@1c21000 {
compatible = allwinner,sun7i-a20-spdif;
reg = 0x01C21000 0x20;
interrupts = 0 13 4;
clocks = apb1_gates 16;
dmas = dma 0 2, dma 0 2;
dma-names = rx, tx;
status = disabled;
}
El 13/06/14 13:22, jonsm...@gmail.com escribió:
What should the clocks be?
Why are there three I2S devices?
Did I get interrupt and DMA values right?
spdif@1c21000 {
compatible = allwinner,sun7i-a20-spdif;
reg = 0x01C21000 0x20;
interrupts = 0 13 4;
clocks = apb1_gates 16;
dmas = dma 0 2, dma 0
I used gate 16 as a filler since I didn't know what to do with them.
This is my current try. It falls over when the codec clock enables. I
will fix up the DMA numbers next.
[ 14.040525] Unable to handle kernel NULL pointer dereference at
virtual address 0036
[ 14.048633] pgd = ed3bc000
[
New diff with the DMA and interrupt fix ups. Now I need to figure out
why the clocks fall over when enabled.
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index bed74a9..a347eff 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++
So correct setting for codec clock is?
codec_clk: clk@01c20140 {
#clock-cells = 0;
compatible = allwinner,sun4i-a10-mod0-clk;
reg = 0x01c20140 0x4;
clocks = pll2 1;
clock-output-names = ir1;
};
And support for pll2 is missing?
--
Jon Smirl
jonsm...@gmail.com
--
You received this message
El 13/06/14 23:55, jonsm...@gmail.com escribió:
So correct setting for codec clock is?
codec_clk: clk@01c20140 {
#clock-cells = 0;
compatible = allwinner,sun4i-a10-mod0-clk;
It does not look like a mod0 to me. User manual shows just 1 bit to gate
the clock, so it should just be a simple gate
Does this look better? Any chance of getting PLL2 support in the near
future since I obviously know very little about the A20 clocks?
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index bed74a9..a347eff 100644
---
