On Sat, 14 Nov 2015 04:36:16 +0800
Vishnu Patekar wrote:
> Hello,
>
> On Fri, Nov 13, 2015 at 7:52 PM, Siarhei Siamashka <
> siarhei.siamas...@gmail.com> wrote:
>
> > On Fri, 13 Nov 2015 11:06:01 +0200
> > Siarhei Siamashka wrote:
>
Hi,
On Mon, Nov 16, 2015 at 4:50 AM, Siarhei Siamashka
wrote:
> On Sat, 14 Nov 2015 04:36:16 +0800
> Vishnu Patekar wrote:
>
>> Hello,
>>
>> On Fri, Nov 13, 2015 at 7:52 PM, Siarhei Siamashka <
>> siarhei.siamas...@gmail.com> wrote:
>>
On Fri, 13 Nov 2015 11:06:01 +0200
Siarhei Siamashka wrote:
> On Fri, 13 Nov 2015 01:12:43 +0800
> Vishnu Patekar wrote:
>
> > Hello,
> >
> > On Thu, Nov 12, 2015 at 7:03 PM, Julian Calaby
> > wrote:
> >
>
On Fri, 13 Nov 2015 01:12:43 +0800
Vishnu Patekar wrote:
> Hello,
>
> On Thu, Nov 12, 2015 at 7:03 PM, Julian Calaby
> wrote:
>
> > Hi Stefan,
> >
> > On Thu, Nov 12, 2015 at 12:20 AM, Stefan Monnier
> > wrote:
Hi Stefan,
On Thu, Nov 12, 2015 at 12:20 AM, Stefan Monnier
wrote:
>> When the CPU clock speed is set to 480 MHz by the U-Boot SPL,
>^^^
> You mean MBUS?
>
>> the performance improvement for 'sunxi-fel write' transfers
>> to DRAM is ~95 KB/s -> ~510 KB/s.
>
Hello,
On Thu, Nov 12, 2015 at 7:03 PM, Julian Calaby
wrote:
> Hi Stefan,
>
> On Thu, Nov 12, 2015 at 12:20 AM, Stefan Monnier
> wrote:
> >> When the CPU clock speed is set to 480 MHz by the U-Boot SPL,
> >^^^
> > You mean MBUS?
>
> When the CPU clock speed is set to 480 MHz by the U-Boot SPL,
^^^
You mean MBUS?
> the performance improvement for 'sunxi-fel write' transfers
> to DRAM is ~95 KB/s -> ~510 KB/s.
> When the CPU clock speed is set to 1008 MHz by the U-Boot SPL,
> the performance improvement for