On Mon, Apr 15, 2019 at 10:22 PM 'Ondřej Jirman' via linux-sunxi
wrote:
>
> Hi ChenYu,
>
> On Mon, Apr 15, 2019 at 04:18:12PM +0800, Chen-Yu Tsai wrote:
> > On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> > wrote:
> > >
> > >
On Mon, Apr 15, 2019 at 10:33 PM Maxime Ripard
wrote:
>
> On Mon, Apr 15, 2019 at 04:22:22PM +0200, Ondřej Jirman wrote:
> > DT would still probably need a re-work in the future, if the PRCM clock
> > modeling the gate would be needed.
>
> Just reacting to that bit.
>
> I know we're pretty bad at
From: Chen-Yu Tsai
The Bananapi M3 and Cubietruck Plus both have USB OTG ports wired to the
SoC and PMIC in the same way, with the N_VBUSEN pin on the PMIC
controlling VBUS output, the PMIC's VBUS input for sensing VBUS, and
PH11 on the SoC for sensing the ID pin.
Enable OTG on both b
From: Quentin Schulz
To prepare for a new PMIC, factor out the code responsible of returning
the maximum current to axp20x_get_current_max.
Signed-off-by: Quentin Schulz
Signed-off-by: Chen-Yu Tsai
---
drivers/power/supply/axp20x_usb_power.c | 52 ++---
1 file changed, 30
From: Chen-Yu Tsai
The VBUS current limit value macros have VBUS typed as VBUC, while
the bitmask macro is named correctly. Fix it.
Fixes: 69fb4dcada77 ("power: Add an axp20x-usb-power driver")
Signed-off-by: Chen-Yu Tsai
---
drivers/power/supply/axp20x_usb_power.c | 16 -
From: Chen-Yu Tsai
On AXP221 and later AXP PMICs that have the N_VBUSEN pin, when this pin
is high, either due to the PMIC driving it high or as an input, the VBUS
detection related interrupt mechanisms are disabled.
Previously this was worked around in the phy-sun4i-usb driver, which
needed to
From: Chen-Yu Tsai
Hi everyone,
This is v4 of my A83T USB power supply / OTG series. Hopefully this is
the last revision even though it's kind of late in the -rc cycle for
the patches to make the next release. Fingers crossed.
Changes since v3:
- Dropped patch for disabling current
From: Quentin Schulz
The AXP813/818 has a VBUS power input. Add a device node for it, now
that we support it.
Signed-off-by: Quentin Schulz
[w...@csie.org: Add commit message]
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/axp81x.dtsi | 4
1 file changed, 4 insertions(+)
diff --git
From: Chen-Yu Tsai
This adds the "x-powers,axp813-usb-power-supply" to the list of
compatibles for AXP20X VBUS power supply driver.
Reviewed-by: Rob Herring
Signed-off-by: Chen-Yu Tsai
---
Changes since v2:
- Collected Rob's Reviewed-by
---
.../devicetree/bindin
From: Quentin Schulz
This adds support for AXP813 PMIC. It is almost the same as AXP22X but
has a different current limit.
Signed-off-by: Quentin Schulz
Signed-off-by: Chen-Yu Tsai
---
drivers/power/supply/axp20x_usb_power.c | 66 -
1 file changed, 65 insertions(+), 1
On Thu, Apr 18, 2019 at 6:27 AM Paul Kocialkowski
wrote:
>
> For our component-backed driver to be properly removed, we need to
> delete the component master in sun4i_drv_remove and make sure to call
> component_unbind_all in the master's unbind so that all components are
> unbound when the master
of_reserved_mem_device_release(dev);
You should probably mention this change in the commit log as well.
Otherwise,
Reviewed-by: Chen-Yu Tsai
> +
> + drm_dev_put(drm);
> }
>
> static const struct component_master_ops sun4i_drv_master_ops = {
> --
> 2.21.0
On Tue, Apr 23, 2019 at 10:06 AM Paul Kocialkowski
wrote:
>
> Hi,
>
> Le vendredi 19 avril 2019 à 19:10 +0200, Paul Kocialkowski a écrit :
> > Hi,
> >
> > On Fri, 2019-04-19 at 09:02 -0700, Chen-Yu Tsai wrote:
> > > On Fri, Apr 19, 2019 at 1:03 AM Paul
On Thu, May 2, 2019 at 3:41 PM Maxime Ripard wrote:
>
> On Tue, Apr 23, 2019 at 02:26:04PM -0300, Pablo Greco wrote:
> > The AP6212 is based on the Broadcom BCM43430 or BCM43438. The WiFi side
> > identifies as BCM43430, while the Bluetooth side identifies as BCM43438.
> >
> > The Bluetooth side i
On Mon, May 13, 2019 at 2:28 AM Jagan Teki wrote:
>
> On Sun, May 12, 2019 at 11:16 PM wrote:
> >
> > From: Clément Péron
> >
> > Enable and add supply to the Mali GPU node on the
> > Pine H64 board.
> >
> > Signed-off-by: Clément Péron
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6-pine-
> >
> > Signed-off-by: Marcus Cooper
>
> Acked-by: Maxime Ripard
Would be nice to have
Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3")
But otherwise,
Acked-by: Chen-Yu Tsai
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cording was somewhat distorted.
> > This was due to the offset not being set correctly on the receiver
> > side.
> >
> > Signed-off-by: Marcus Cooper
>
> Acked-by: Maxime Ripard
Would be nice to have
Fixes: 7d2993811a1e ("ASoC: sun4i-i2s: Add support for H3")
On Tue, Jun 4, 2019 at 1:47 AM wrote:
>
> From: Marcus Cooper
>
> On the newer SoCs this is set by default to transfer a 0 after
> each sample in each slot. However the platform that this driver
> was developed on had the default setting where it padded the
> audio gain with zeros. This isn't a p
> Signed-off-by: Jagan Teki
Acked-by: Chen-Yu Tsai
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To view
> Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu Tsai
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T
umbers, for more code
> readability.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu Tsai
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to
Use the existing macros, instead of real numbers for more
> code readability.
>
> Signed-off-by: Jagan Teki
Reviewed-by: Chen-Yu Tsai
However, you might want to rename the clock first, then switch to
using the index macros?
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On Fri, Jun 14, 2019 at 11:19 AM Chen-Yu Tsai wrote:
>
> On Fri, Jun 14, 2019 at 2:53 AM Jagan Teki wrote:
> >
> > TCON LCD0, LCD1 in allwinner R40, are used for managing
> > LCD interfaces like RGB, LVDS and DSI.
> >
> > Like TCON TV0, TV1 these LCD0, LC
On Fri, Jun 14, 2019 at 2:54 AM Jagan Teki wrote:
>
> According to Fig 7-2. TCON Top Block Diagram in User manual.
>
> TCON TOP can have an hierarchy for TCON_LCD0, LCD1 like
> TCON_TV0, TV1 so, the tcon top would handle the clocks of
> TCON_LCD0, LCD1 similar like TV0, TV1.
That is not guarantee
On Fri, Jun 14, 2019 at 5:48 PM Jagan Teki wrote:
>
> On Fri, Jun 14, 2019 at 9:16 AM Chen-Yu Tsai wrote:
> >
> > On Fri, Jun 14, 2019 at 2:54 AM Jagan Teki
> > wrote:
> > >
> > > According to Fig 7-2. TCON Top Block Diagram in User manual.
>
On Fri, Jun 14, 2019 at 6:56 PM Jagan Teki wrote:
>
> On Fri, Jun 14, 2019 at 9:05 AM Chen-Yu Tsai wrote:
> >
> > On Fri, Jun 14, 2019 at 11:19 AM Chen-Yu Tsai wrote:
> > >
> > > On Fri, Jun 14, 2019 at 2:53 AM Jagan Teki
> > > wrote:
> > >
On Sat, Jun 15, 2019 at 12:44 AM Jagan Teki wrote:
>
> TCON TOP have clock gates for TV0, TV1, dsi and right
> now these are register during bind call.
>
> Of which, dsi clock gate would required during DPHY probe
> but same can miss to get since tcon top is not bound at
> that time.
>
> To solve,
On Mon, Jun 17, 2019 at 12:31 AM Corentin Labbe
wrote:
>
> Hello
>
> This serie fix building sun8i-emac for a83t and then enable networking
> for BananaPi M3.
>
> Regards
>
> Corentin Labbe (3):
> configs: Sinovoip_BPI_M3_defconfig: Fix invalid DLDO3 settings
> net: sun8i-emac: bring back supp
On Mon, Jun 17, 2019 at 7:45 PM Maxime Ripard wrote:
>
> On Fri, Jun 14, 2019 at 10:13:20PM +0530, Jagan Teki wrote:
> > TCON TOP have clock gates for TV0, TV1, dsi and right
> > now these are register during bind call.
> >
> > Of which, dsi clock gate would required during DPHY probe
> > but same
On Mon, Jun 17, 2019 at 6:30 PM Jagan Teki wrote:
>
> On Sun, Jun 16, 2019 at 11:01 AM Chen-Yu Tsai wrote:
> >
> > On Sat, Jun 15, 2019 at 12:44 AM Jagan Teki
> > wrote:
> > >
> > > TCON TOP have clock gates for TV0, TV1, dsi and right
>
On Tue, Jun 18, 2019 at 3:12 PM Jagan Teki wrote:
>
> On Mon, Jun 17, 2019 at 6:31 PM Chen-Yu Tsai wrote:
> >
> > On Mon, Jun 17, 2019 at 7:45 PM Maxime Ripard
> > wrote:
> > >
> > > On Fri, Jun 14, 2019 at 10:13:20PM +0530, Jagan Teki wrote:
> >
On Tue, Jun 18, 2019 at 3:45 PM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 12:49 PM Chen-Yu Tsai wrote:
> >
> > On Mon, Jun 17, 2019 at 6:30 PM Jagan Teki
> > wrote:
> > >
> > > On Sun, Jun 16, 2019 at 11:01 AM Chen-Yu Tsai wrote:
> > > &g
On Tue, Jun 18, 2019 at 6:34 PM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 1:23 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jun 18, 2019 at 3:45 PM Jagan Teki
> > wrote:
> > >
> > > On Tue, Jun 18, 2019 at 12:49 PM Chen-Yu Tsai wrote:
> > > &
On Tue, Jun 18, 2019 at 6:51 PM Jagan Teki wrote:
>
> On Fri, Jun 14, 2019 at 8:15 PM Maxime Ripard
> wrote:
> >
> > On Fri, Jun 14, 2019 at 12:03:13PM +0530, Jagan Teki wrote:
> > > On Thu, Jun 13, 2019 at 6:56 PM Maxime Ripard
> > > wrote:
> > > >
> > > > On Wed, Jun 05, 2019 at 01:17:11PM +
On Tue, Jun 18, 2019 at 8:11 PM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 5:13 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jun 18, 2019 at 6:51 PM Jagan Teki
> > wrote:
> > >
> > > On Fri, Jun 14, 2019 at 8:15 PM Maxime Ripard
> > > wrote:
On Wed, Jun 19, 2019 at 1:17 AM Jernej Škrabec wrote:
>
> Dne torek, 18. junij 2019 ob 19:13:16 CEST je Clément Péron napisal(a):
> > Hi,
> >
> > On Thu, 16 May 2019 at 03:27, Andre Przywara wrote:
> > > The first USB controller on the H6 SoC shares a PHY with the OTG
> > > controller. Reportedly
On Fri, Jun 21, 2019 at 2:51 AM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 8:15 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jun 18, 2019 at 8:11 PM Jagan Teki
> > wrote:
> > >
> > > On Tue, Jun 18, 2019 at 5:13 PM Chen-Yu Tsai wrote:
> > > &
On Fri, Jun 21, 2019 at 12:24 AM Jagan Teki wrote:
>
> On Tue, Jun 18, 2019 at 4:24 PM Chen-Yu Tsai wrote:
> >
> > On Tue, Jun 18, 2019 at 6:34 PM Jagan Teki
> > wrote:
> > >
> > > On Tue, Jun 18, 2019 at 1:23 PM Chen-Yu Tsai wrote:
> > > &
On Fri, May 24, 2019 at 6:27 PM Jagan Teki wrote:
>
> On Fri, May 24, 2019 at 2:18 AM Maxime Ripard
> wrote:
> >
> > On Mon, May 20, 2019 at 02:33:10PM +0530, Jagan Teki wrote:
> > > The current code is computing vertical video start delay as
> > >
> > > delay = mode->vtotal - (mode->vsync_end -
On Thu, Jun 20, 2019 at 9:02 AM Andre Przywara wrote:
>
> In recent Allwinner SoCs the first USB host controller (HCI0) shares
> the first PHY with the MUSB controller. Probably to make this sharing
> work, we were avoiding to declare this in the DT. This has two
> shortcomings:
> - U-Boot (which
Hi,
On Mon, May 20, 2019 at 5:07 PM Jagan Teki wrote:
>
> start value in video start delay computation done in below commit
> is as per the legacy bsp drivers/video/sunxi/legacy..
> "drm/sun4i: dsi: Change the start delay calculation"
> (sha1: da676c6aa6413d59ab0a80c97bbc273025e640b2)
There is a
On Mon, Jun 24, 2019 at 8:58 PM Andre Przywara wrote:
>
> On Mon, 24 Jun 2019 16:25:47 +0800
> Chen-Yu Tsai wrote:
>
> Hi,
>
> > On Thu, Jun 20, 2019 at 9:02 AM Andre Przywara
> > wrote:
> > >
> > > In recent Allwinner SoCs the first USB host c
On Mon, Jun 24, 2019 at 9:03 PM Chen-Yu Tsai wrote:
>
> On Mon, Jun 24, 2019 at 8:58 PM Andre Przywara wrote:
> >
> > On Mon, 24 Jun 2019 16:25:47 +0800
> > Chen-Yu Tsai wrote:
> >
> > Hi,
> >
> > > On Thu, Jun 20, 2019 at 9:02 AM Andr
er:
> $ grep -i -e "^&ahci" arch/arm/boot/dts/sun*dts
> and http://linux-sunxi.org/SATA#Devices_with_SATA_ports
> See also http://linux-sunxi.org/Category:Devices_with_SATA_port
>
> Acked-by: Maxime Ripard
> Reviewed-by: Hans de Goede
> Signed-off-by: Uen
Hi,
On Thu, Jul 11, 2019 at 11:46 PM Marc Haber wrote:
>
> On Wed, Jul 10, 2019 at 10:50:35PM +0200, Marc Haber wrote:
> > and the running system has no network interface. Suspicious entries
> > would be:
> >
> > |Jul 10 22:39:15 entrada kernel: [6.510668] sun7i-dwmac
> > 1c5.ethernet: P
On Sat, Jul 27, 2019 at 6:46 PM Maxime Ripard wrote:
>
> Hi,
>
> On Fri, Jul 26, 2019 at 08:40:42PM +0200, Jernej Skrabec wrote:
> > H6 PWM core needs bus clock to be enabled in order to work.
> >
> > Add a quirk for it.
> >
> > Signed-off-by: Jernej Skrabec
> > ---
> > drivers/pwm/pwm-sun4i.c |
On Sat, Jul 27, 2019 at 10:28 PM Jernej Škrabec wrote:
>
> Dne sobota, 27. julij 2019 ob 12:50:08 CEST je Maxime Ripard napisal(a):
> > On Fri, Jul 26, 2019 at 08:40:44PM +0200, Jernej Skrabec wrote:
> > > PWM core has an option to bypass whole logic and output unchanged source
> > > clock as PWM
On Mon, Jul 29, 2019 at 2:36 PM Uwe Kleine-König
wrote:
>
> Cc += reset framework maintainer
>
> Hello Jernej,
>
> On Fri, Jul 26, 2019 at 08:40:41PM +0200, Jernej Skrabec wrote:
> > H6 PWM core needs deasserted reset line in order to work.
> >
> > Add a quirk for it.
> >
> > Signed-off-by: Jernej
On Tue, Jul 30, 2019 at 12:07 AM Uwe Kleine-König
wrote:
>
> On Mon, Jul 29, 2019 at 05:55:52PM +0200, Jernej Škrabec wrote:
> > Hi Uwe,
> >
> > Dne ponedeljek, 29. julij 2019 ob 08:40:30 CEST je Uwe Kleine-König
> > napisal(a):
> > > On Fri, Jul 26, 2019 at 08:40:43PM +0200, Jernej Skrabec wrote:
, 29. julij 2019 ob 20:40:41 CEST je Uwe Kleine-König
> > > > napisal(a):
> > > > > On Mon, Jul 29, 2019 at 06:40:15PM +0200, Jernej Škrabec wrote:
> > > > > > Dne ponedeljek, 29. julij 2019 ob 18:24:28 CEST je Uwe Kleine-König
> > > > > >
-by: Stefan Mavrodiev
Acked-by: Chen-Yu Tsai
And for single patches, you don't need to write a separate cover letter.
Just put whatever you need to add after the "---" separator.
> ---
> drivers/nvmem/sunxi_sid.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --
On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
wrote:
>
> From: Ondrej Jirman
>
> RTC on H6 is mostly the same as on H5 and H3. It has slight differences
> mostly in features that are not yet supported by this driver.
>
> Some differences are already stated in the comments in existing cod
scillator. Add new
> compatible for this RTC.
>
> Signed-off-by: Ondrej Jirman
Acked-by: Chen-Yu Tsai
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On Mon, Aug 5, 2019 at 6:45 PM Ondřej Jirman wrote:
>
> On Mon, Aug 05, 2019 at 06:16:14PM +0800, Chen-Yu Tsai wrote:
> > On Fri, Apr 12, 2019 at 8:07 PM megous via linux-sunxi
> > wrote:
> > >
> > > From: Ondrej Jirman
> > >
> > > RTC o
On Mon, Aug 5, 2019 at 7:10 PM Ondřej Jirman wrote:
>
> On Mon, Aug 05, 2019 at 06:54:17PM +0800, Chen-Yu Tsai wrote:
> > On Mon, Aug 5, 2019 at 6:45 PM Ondřej Jirman wrote:
> > >
> > > On Mon, Aug 05, 2019 at 06:16:14PM +0800, Chen-Yu Tsai wrote:
> > > &
On Thu, Aug 1, 2019 at 1:32 PM Jernej Škrabec wrote:
>
> Dne sreda, 31. julij 2019 ob 14:29:53 CEST je Maxime Ripard napisal(a):
> > On Tue, Jul 30, 2019 at 07:57:10PM +0200, Jernej Škrabec wrote:
> > > Dne torek, 04. junij 2019 ob 11:38:44 CEST je Code Kipper napisal(a):
> > > > On Tue, 4 Jun 201
On Wed, Aug 7, 2019 at 6:55 PM Alexandre Belloni
wrote:
>
> Hi,
>
> On 06/08/2019 20:30:45+0200, Ondřej Jirman wrote:
> > Maybe whether XO or DCXO is used also matters if you want to do some fine
> > tunning of DCXO (control register has pletny of options), but that's
> > probably
> > better done
Hi,
On Mon, Aug 12, 2019 at 4:31 AM Clément Péron wrote:
>
> The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio).
>
> Only one pinmuxing is available so set it as default.
>
> Signed-off-by: Clément Péron
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38
On Mon, Aug 12, 2019 at 12:52 PM Chen-Yu Tsai wrote:
>
> Hi,
>
> On Mon, Aug 12, 2019 at 4:31 AM Clément Péron wrote:
> >
> > The Allwinner H6 has a SPDIF controller called OWA (One Wire Audio).
> >
> > Only one pinmuxing is available so set it as default.
On Mon, Aug 12, 2019 at 4:32 AM Clément Péron wrote:
>
> Allwinner A64 and H6 use the Sun4i SPDIF driver.
>
> Enable this to allow a proper support.
>
> Signed-off-by: Clément Péron
Applied. Thanks.
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On Mon, Aug 12, 2019 at 3:45 PM Jernej Škrabec wrote:
>
> Dne torek, 06. avgust 2019 ob 17:57:39 CEST je meg...@megous.com napisal(a):
> > From: Ondrej Jirman
> >
> > This series implements support for Xunlong Orange Pi 3 board. There
> > are only a few patches remaining.
> >
> > - ethernet suppo
On Tue, Aug 6, 2019 at 11:57 PM wrote:
>
> From: Ondrej Jirman
>
> Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
> to the phy datasheet, both regulators need to be enabled at the same time,
> but we can only specify a single phy-supply in the DT.
>
> This can be achiev
On Wed, Aug 14, 2019 at 2:09 PM wrote:
>
> From: Marcus Cooper
>
> Bypass the regmap cache when flushing the i2s FIFOs and modify the tables
> to reflect this.
>
> Signed-off-by: Marcus Cooper
> ---
> sound/soc/sunxi/sun4i-i2s.c | 31 ++-
> 1 file changed, 10 inserti
On Wed, Aug 14, 2019 at 2:09 PM wrote:
>
> From: Jernej Skrabec
>
> I2S doesn't work if parent rate couldn't be change. Difference between
> wanted and actual rate is too big.
>
> Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.
>
> Signed-off-by: Jernej Skrabec
This lacks your SoB. P
On Wed, Aug 21, 2019 at 1:52 PM Code Kipper wrote:
>
> ThanksI've added to my next patch series but if you could add it
> when applying that would be great.
Please reply with an explicit SoB to put it on the record.
ChenYu
> BR,
> CK
>
> On Wed, 21 Aug 2019 at
On Wed, Aug 21, 2019 at 5:19 PM Code Kipper wrote:
>
> On Wed, 14 Aug 2019 at 08:09, wrote:
> >
> > From: Jernej Skrabec
> >
> > I2S doesn't work if parent rate couldn't be change. Difference between
> > wanted and actual rate is too big.
> >
> > Fix this by adding CLK_SET_RATE_PARENT flag to I2
On Wed, Aug 21, 2019 at 7:54 PM Alejandro González
wrote:
>
> This change exposes the needed interfaces to configure wake alarms to
> userspace, but it doesn't let a SoC resume from a wakealarm by itself
> (that depends on how interrupts are handled). However, it is still
> useful for generating i
On Tue, Aug 27, 2019 at 2:07 AM wrote:
>
> From: Marcus Cooper
>
> The regmap configuration is set up for the legacy block on the
> A83T whereas it uses the new block with a larger register map.
Looking at the code Allwinner previously released [1], that doesn't seem to be
the case. Keep in mind
On Tue, Aug 27, 2019 at 1:55 PM Code Kipper wrote:
>
> On Tue, 27 Aug 2019 at 06:13, Chen-Yu Tsai wrote:
> >
> > On Tue, Aug 27, 2019 at 2:07 AM wrote:
> > >
> > > From: Marcus Cooper
> > >
> > > The regmap configuration is set up for the
On Tue, Aug 27, 2019 at 4:35 PM Code Kipper wrote:
>
> On Tue, 27 Aug 2019 at 10:01, Chen-Yu Tsai wrote:
> >
> > On Tue, Aug 27, 2019 at 1:55 PM Code Kipper wrote:
> > >
> > > On Tue, 27 Aug 2019 at 06:13, Chen-Yu Tsai wrote:
> > > >
On Wed, Aug 28, 2019 at 8:52 PM Linus Walleij wrote:
>
> On Sun, Aug 25, 2019 at 5:06 PM Alejandro González
> wrote:
>
> > Jernej Skrabec compared the BSP driver with this
> > driver, and found that the BSP driver configures pinctrl to operate at
> > 1.8 V when entering DDR mode (although 3.3 V o
On Wed, Aug 28, 2019 at 9:43 PM Maxime Ripard wrote:
>
> On Wed, Aug 28, 2019 at 09:29:32PM +0800, Chen-Yu Tsai wrote:
> > On Wed, Aug 28, 2019 at 8:52 PM Linus Walleij
> > wrote:
> > >
> > > On Sun, Aug 25, 2019 at 5:06 PM Alejandro González
> > >
s/class/rtc/rtc0/wakealarm && sleep 5 && grep rtc
> /proc/interrupts
> 29: 1 0 0 0 GICv2 133 Level
> 700.rtc
>
> Signed-off-by: Alejandro González
This seems like standard PM stuff. Nothing sunxi-specific.
FWIW,
On Thu, Sep 12, 2019 at 10:37 AM Maxime Ripard wrote:
>
> Hi Corentin,
>
> On Wed, Sep 11, 2019 at 08:31:58PM +0200, Corentin Labbe wrote:
> > On Sat, Sep 07, 2019 at 07:01:16AM +0300, Maxime Ripard wrote:
> > > On Fri, Sep 06, 2019 at 08:45:45PM +0200, Corentin Labbe wrote:
> > > > This patch add
On Thu, Sep 12, 2019 at 9:33 PM Maxime Ripard wrote:
>
> On Thu, Sep 12, 2019 at 09:26:27PM +0100, Chen-Yu Tsai wrote:
> > > >
> > > > clock-names:
> > > > items:
> > > > - const: ahb
> > > > - c
On Sat, Sep 14, 2019 at 9:51 PM Jernej Skrabec wrote:
>
> Audio devices needs exact clock rates in order to correctly reproduce
> the sound. Until now, only integer factors were used to configure H6
> audio PLL which resulted in inexact rates. Fix that by adding support
> for fractional factors us
On Wed, Sep 18, 2019 at 1:21 PM Jernej Škrabec wrote:
>
> Dne torek, 17. september 2019 ob 08:54:08 CEST je Chen-Yu Tsai napisal(a):
> > On Sat, Sep 14, 2019 at 9:51 PM Jernej Skrabec
> wrote:
> > > Audio devices needs exact clock rates in order to correctly reproduce
&g
On Fri, Sep 20, 2019 at 4:32 PM Priit Laes wrote:
>
> Heya!
>
> I have seen following warning message for few times when shutting down the
> machine (Olinuxino Lime2-emmc) running the mainline kernel.
>
> [snip]
> WARNING: CPU: 0 PID: 1 at drivers/i2c/i2c-core.h:41 i2c_transfer+0xe8/0xf4
> No atom
si.h
> index 5c3ad5be0690..a01d44e9e461 100644
> --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
> @@ -12,6 +12,7 @@
> #include
> #include
> #include
> +#include
You don't need to include the header file since you
On Sun, Aug 25, 2019 at 1:50 AM Samuel Holland wrote:
>
> The RSB controller has two registers for controlling interrupt inputs:
> RSB_INTE, which has bits for each possible interrupt, and the global
> interrupt enable bit in RSB_CTRL.
>
> Currently, we enable the bits in RSB_INTE before each tran
Hi,
On Wed, Oct 2, 2019 at 7:27 PM Icenowy Zheng wrote:
>
> AXP813 PMIC has two Vbus maximum value settings -- one is the default
> value, which is currently the only supported one; the other is the
> really applied value, which is set according to the default value if the
> BC detection module d
On Tue, Oct 8, 2019 at 11:09 AM Icenowy Zheng wrote:
> 于 2019年10月8日 GMT+08:00 上午12:07:05, Chen-Yu Tsai 写到:
> >Hi,
> >
> >On Wed, Oct 2, 2019 at 7:27 PM Icenowy Zheng wrote:
> >>
> >> AXP813 PMIC has two Vbus maximum value settings -- one is the default
ot;ARM: sun8i: smp: Add support for A83T")
> Signed-off-by: Ondrej Jirman
> Cc: sta...@vger.kernel.org
Acked-by: Chen-Yu Tsai
Though I distinctly remember the BSP had some code dealing with chip
revisions in which the two bits were reversed. :(
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Hi,
On Fri, Nov 1, 2019 at 1:58 AM Georgii Staroselskii
wrote:
>
> The Emlid Neutis N5 board has AP6212 BT+WiFi chip. This patch is in
> line with 8558c6e2 and other commits that add Bluetooth support for
The proper format for mentioning other commits is
commit <12-character git hash prefix
On Thu, Nov 28, 2019 at 11:06 AM Ondřej Jirman wrote:
>
> Hi,
>
> On Thu, Nov 28, 2019 at 10:26:08AM +0800, Yong wrote:
> > Hi Ondrej,
> >
> > This has been discussed.
> > And Maxime sent a patch for this:
> > https://www.mail-archive.com/linux-media@vger.kernel.org/msg127149.html
>
> Thanks for p
On Thu, Nov 28, 2019 at 11:51 AM Ondřej Jirman wrote:
>
> On Thu, Nov 28, 2019 at 11:26:24AM +0800, Chen-Yu Tsai wrote:
> > On Thu, Nov 28, 2019 at 11:06 AM Ondřej Jirman wrote:
> > >
> > > Hi,
> > >
> > > On Thu, Nov 28, 2019 at
On Fri, Nov 29, 2019 at 3:22 PM Stefan Mavrodiev wrote:
>
>
> On 11/28/19 12:33 PM, Maxime Ripard wrote:
> Hi Maxime,
> > Hi Stefan,
> >
> > On Wed, Nov 27, 2019 at 09:07:40AM +0200, Stefan Mavrodiev wrote:
> >> On 11/26/19 6:27 PM, Maxime Ripard wrote:
> >>> Hi Stefan,
> >>>
> >>> On Tue, Nov 26,
On Fri, Nov 29, 2019 at 5:14 PM Stefan Mavrodiev wrote:
>
> A64-OLinuXino-eMMC uses 1.8V for eMMC supply. This is done via a triple
> jumper, which sets VCC-PL to either 1.8V or 3.3V. This setting is different
> for boards with and without eMMC.
>
> This is not a big issue for DDR52 mode, however
Hi,
On Fri, Nov 29, 2019 at 5:14 PM Stefan Mavrodiev wrote:
>
> This patch serie updates bank regulators for A64-OLinuXino and
> A64-OLinuXino-eMMC.
>
> Also, eMMC supply is changed to ELDO1, which is the actual one. The same is
> done for the SDIO card - ALDO2 is changed to DCDC1.
>
>
> Stefan M
On Tue, Dec 3, 2019 at 9:48 PM Jagan Teki wrote:
>
> As per the user manual, look like mod clock is not mandatory
> for all Allwinner MIPI DSI controllers, it is connected to
> CLK_DSI_SCLK for A31 and not available in A64.
>
> So add has_mod_clk quirk and process the mod clk accordingly.
>
> Test
ak, like other EHCI/OHCI pairs in Allwinner SoCs.
>
> Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
>
> Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
Please keep acks and review tags from others if you haven't changed the
patch.
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On Wed, Mar 15, 2017 at 5:09 PM, Icenowy Zheng wrote:
>
> 2017年3月15日 15:16于 Chen-Yu Tsai 写道：
>>
>> Hi,
>>
>> On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng wrote:
>> > Orange Pi Zero board features a USB OTG port, which has a ID pin, and
>> > can
board.
>
> Add support for this port.
>
> Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
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hich is very likely to crash the CPU.
>
> Therefore, these two frequencies must be enabled on a per-board basis.
>
> Signed-off-by: Quentin Schulz
Acked-by: Chen-Yu Tsai
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To
> This patch applies the operating points to each cpu of the A33.
>
This should have
Fixes: 03749eb88e63 ("ARM: dts: sun8i: add opp-v2 table for A33")
and be merged as fixes for 4.11.
> Signed-off-by: Quentin Schulz
Acked-by: Chen-Yu Tsai
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On Tue, Mar 21, 2017 at 11:36 PM, Quentin Schulz
wrote:
> This adds the cpu-supply DT property to the cpu0 DT node needed by
> the board to adapt the regulator voltage depending on the currently used
> OPP.
>
> Signed-off-by: Quentin Schulz
Acked-by: Chen-Yu Tsai
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> This adds support for most of AXP20X and AXP22X ADCs.
>
> Signed-off-by: Quentin Schulz
> Acked-by: Maxime Ripard
> Acked-by: Chen-Yu Tsai
> Reviewed-by: Jonathan Cameron
This patch seems to depend on commit 4707274714ef ("mfd: axp20x: Correct name
of temperature data A
The SinA31s has a coaxial SPDIF output. Enable it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31s-sina31s.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts
index
On Thu, Mar 23, 2017 at 5:35 PM, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Mar 22, 2017 at 12:34:45PM +0800, Chen-Yu Tsai wrote:
>> P.S. I'm thinking about having MFD_AXP20X imply its various sub-drivers.
>> Not sure if that was the intended usage of the new imply
er up external USB devices.
>
> Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
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