On Wed, Sep 30, 2015 at 4:52 PM, Lucas Stach wrote:
> Am Mittwoch, den 30.09.2015, 10:17 +0800 schrieb Peter Chen:
>> It can improve the USB performance when choosing larger
>> burst size at some systems (bus size is larger), there is
>> no side effect if this burst size
On Wed, Sep 30, 2015 at 07:12:18PM +0200, Nicolas Ferre wrote:
>
> > Sorry that I missed ccing you while sending the patch. We should not
> > always depend on getmaintainer.pl.
>
> Well, I'm marked as maintainer for this drivers actually and
> get_maintainer.pl shouldn't lie this time...
For
> From: Mian Yousaf Kaukab
> Date: Tue, Sep 29, 2015 at 12:25 PM
> Subject: [PATCH v1 Resend] usb: dwc2: gadget: fix a memory use-after-free bug
> To: linux-usb@vger.kernel.org, ba...@ti.com, john.y...@synopsys.com,
> l...@rock-chips.com
> Cc: he...@sntech.de,
On 29/09/15 04:01, Chunfeng Yun wrote:
There some vendor quirks for MTK xhci host controller:
1. It defines some extra SW scheduling parameters for HW
to minimize the scheduling effort for synchronous and
interrupt endpoints. The parameters are put into reseved
DWs of slot context and
On Thu, Oct 1, 2015 at 4:42 PM, Lucas Stach wrote:
> Am Donnerstag, den 01.10.2015, 16:13 +0800 schrieb Peter Chen:
>> On Wed, Sep 30, 2015 at 4:52 PM, Lucas Stach wrote:
>> > Am Mittwoch, den 30.09.2015, 10:17 +0800 schrieb Peter Chen:
>> >> It
http://www.amazon.com/gp/product/B014SO7U4W
This book provides a bootstrap session on how this new technology can
seamlessly integrate into the existing USB ecosystem and also how it
can integrate into new ecosystems and create new markets.
Who is this book for?
This book is for any engineering
On Mon, Sep 21, 2015 at 12:16:12PM +0200, Marek Szyprowski wrote:
> DWC2 module on some platforms needs three additional hardware
> resources: phy controller, clock and power supply. All of them must be
> enabled/activated to properly initialize and operate. This was initially
> handled in
On Thu, Oct 01, 2015 at 10:50:18AM -0500, Felipe Balbi wrote:
> On Mon, Sep 21, 2015 at 12:16:12PM +0200, Marek Szyprowski wrote:
> > DWC2 module on some platforms needs three additional hardware
> > resources: phy controller, clock and power supply. All of them must be
> > enabled/activated to
On Thu, Oct 01, 2015 at 12:01:48PM +, Kaukab, Yousaf wrote:
> > From: Mian Yousaf Kaukab
> > Date: Tue, Sep 29, 2015 at 12:25 PM
> > Subject: [PATCH v1 Resend] usb: dwc2: gadget: fix a memory use-after-free
> > bug
> > To: linux-usb@vger.kernel.org, ba...@ti.com,
If a device supports usb 3.1 SupeerSpeedPlus Gen2 speeds it povides
a SuperSpeedPlus device capability descriptor as a part of its
BOS descriptor. If we find one while parsing the BOS then save it
togeter with the other device capabilities found in the BOS
Signed-off-by: Mathias Nyman
Set the controller speed to HCD_USB31 to if host hardware supports USB 3.1
For PCI xhci controllers the USB 3.1 support is checked from SBRN bits in
pci config space. Platform controllers will need to set xhci->sbrn == 0x31
to indicate USB 3.1 support before calling xhci_gen_setup().
Also make
xhci 1.1 controllers that support USB 3.1 must provide a protocol speed ID
(PSI) list to inform the driver of the supported speeds.
The PSI list can be read from the xhci supported protocol extended
capabilities.
The PSI values will be used to create a USB 3.1 SuperSpeedPlus capability
descriptor
From: Lu Baolu
xhci 1.1 capable controllers have a new HCCPARAMS2 registers
with bits indicating support for new xhci 1.1 capabilities.
Also add support for the new xhci 1.1 bits in the config operational
opertational register that used to be reserved
Signed-off-by:
USB 3.1 adds different types of Get Port Status request.
The Get Extended Port Status request returns 4 additional bytes
after the normal portstatus and portchange words containing
link speed and lane information about a connected enhanced super
speed device
Signed-off-by: Mathias Nyman
USB 3.1 capable xhci controllers use a new default speed ID "5" in the
PORTSC register to represent a 10Gbps connection speed of a SuperSpeedPlus
device
Make sure the xhci driver can handle the returned SuperSpeedPlus speed ID
properly
Signed-off-by: Mathias Nyman
All usb devices that support USB 3.1 Gen2 speeds need to provide a
SuperSpeedPlus device capability descriptor as part of their BOS
descriptor.
If the xhci controller supports USB 3.1 enhanced SuperSpeed, meaning
it can handle both Gen1 SuperSpeed 5Gbps and Gen2 SuperSpeedPlus 10Gbps
devices,
USB 3.1 SuperSpeedPlus device capability descriptor is returned as part
of the bos descriptor for devices that support SuperSpeedPlus protocol.
The descriptor contains more detailed information about the supported
speeds of the device. More details about the descriptor can be found in
the USB 3.1
This patchseries adds the USB 3.1 groundwork.
USB 3.1 specification includes a new SuperSpeedPlus protocol supporting
up to 10Gbps speeds. USB 3.1 devices using the new SuperSpeedPlus protocol
are called USB 3.1 Gen2 devices.
Devices announce their SuperSpeedPlus capability with a new
Hosts that support USB 3.1 Enhaned SuperSpeed can set their speed to
HCD_USB31 to let usb core and host drivers know that the controller
supports new USB 3.1 features.
make sure usb core handle HCD_USB31 hosts correctly, for now similar
to HCD_USB3.
Signed-off-by: Mathias Nyman
On Wed, Sep 30, 2015 at 06:34:28PM +0200, Nicolas Ferre wrote:
> Le 30/09/2015 18:24, Sudip Mukherjee a écrit :
> > On Wed, Sep 30, 2015 at 11:04:54AM -0500, Felipe Balbi wrote:
> >> On Wed, Sep 23, 2015 at 09:22:48PM +0530, Sudip Mukherjee wrote:
> >>> On Mon, Sep 21, 2015 at 04:40:57PM +0530,
Hi,
On Mon, Sep 28, 2015 at 03:33:28PM +0200, Christoph Hellwig wrote:
> The Subject line is part of the commit log. If you have a useful
heh
> suggestion for improving the logs please feel free to suggest it.
how about explaining why you want per-attribute show/store methods ?
--
balbi
On Thu, Oct 01, 2015 at 12:58:49PM -0500, Felipe Balbi wrote:
> Hi,
>
> On Thu, Oct 01, 2015 at 06:43:08PM +0100, Mark Brown wrote:
> > On Thu, Oct 01, 2015 at 12:29:32PM -0500, Felipe Balbi wrote:
> >
> > > Frankly, I wanted all of this to be decided in userland with the
> > > kernel just
On Thu, Sep 24, 2015 at 10:39:23AM -0700, Baolin Wang wrote:
> The usb charger framework is based on usb gadget. The usb charger
> need to be notified the state changing of usb gadget to confirm the
> usb charger state.
>
> Thus this patch adds a notifier mechanism for usb gadget to report a
>
On Thu, Oct 01, 2015 at 12:29:32PM -0500, Felipe Balbi wrote:
> Frankly, I wanted all of this to be decided in userland with the
> kernel just providing notification and basic safety checks (we don't
> want to allow a bogus userspace daemon frying anybody's devices).
What's the advantage of
Hi,
On Thu, Oct 01, 2015 at 06:43:08PM +0100, Mark Brown wrote:
> On Thu, Oct 01, 2015 at 12:29:32PM -0500, Felipe Balbi wrote:
>
> > Frankly, I wanted all of this to be decided in userland with the
> > kernel just providing notification and basic safety checks (we don't
> > want to allow a
John,
On Tue, Aug 18, 2015 at 5:19 PM, John Youn wrote:
> Hi Yunzhi,
>
> My concern is with the delays due to calling the dwc2_core_reset
> during probe. You could factor out the assertion of the core
> soft reset from the dwc2_core_reset and just use that before
>
Sometimes since updating to kernel 4.1 and now also with 4.2 usb
doesn't work anymore, and dmesg shows this stuff. I then have to
reboot to fix it. Does anyone have a recommendation for me?
I can provide more information if required and also test patches, but
it's very hard to reproduce this.
I
On 10/1/2015 8:50 AM, Felipe Balbi wrote:
> On Mon, Sep 21, 2015 at 12:16:12PM +0200, Marek Szyprowski wrote:
>> DWC2 module on some platforms needs three additional hardware
>> resources: phy controller, clock and power supply. All of them must be
>> enabled/activated to properly initialize and
Add a device quirk for the Logitech PTZ Pro Camera and its sibling the
ConferenceCam CC3000e Camera.
This fixes the failed camera enumeration on some boot, particularly on
machines with fast CPU.
Tested by connecting a Logitech PTZ Pro Camera to a machine with a
Haswell Core i7-4600U CPU @
On Thu, Oct 01, 2015 at 09:04:59PM +, John Youn wrote:
> On 10/1/2015 8:50 AM, Felipe Balbi wrote:
> > On Mon, Sep 21, 2015 at 12:16:12PM +0200, Marek Szyprowski wrote:
> >> DWC2 module on some platforms needs three additional hardware
> >> resources: phy controller, clock and power supply.
On 10/1/2015 3:04 PM, Felipe Balbi wrote:
> On Thu, Oct 01, 2015 at 09:04:59PM +, John Youn wrote:
>> On 10/1/2015 8:50 AM, Felipe Balbi wrote:
>>> On Mon, Sep 21, 2015 at 12:16:12PM +0200, Marek Szyprowski wrote:
DWC2 module on some platforms needs three additional hardware
On Thu, Oct 01, 2015 at 10:21:22PM +, John Youn wrote:
> On 10/1/2015 3:04 PM, Felipe Balbi wrote:
> > On Thu, Oct 01, 2015 at 09:04:59PM +, John Youn wrote:
> >> On 10/1/2015 8:50 AM, Felipe Balbi wrote:
> >>> On Mon, Sep 21, 2015 at 12:16:12PM +0200, Marek Szyprowski wrote:
> DWC2
> -Original Message-
> From: Felipe Balbi [mailto:ba...@ti.com]
> Sent: Wednesday, September 30, 2015 6:24 PM
> To: Kaukab, Yousaf
> Cc: linux-usb@vger.kernel.org; ba...@ti.com; john.y...@synopsys.com;
> Herrero, Gregory; he...@sntech.de; diand...@chromium.org;
> r.bald...@samsung.com;
> -Original Message-
> From: Felipe Balbi [mailto:ba...@ti.com]
> Sent: Wednesday, September 30, 2015 6:26 PM
> To: Sergei Shtylyov
> Cc: Kaukab, Yousaf; linux-usb@vger.kernel.org; ba...@ti.com;
> john.y...@synopsys.com; Herrero, Gregory; he...@sntech.de;
> diand...@chromium.org;
From: Roman Bacik
USB OTG driver in isochronous mode has to set the parity of the receiving
microframe. The parity is set to even by default. This causes problems for
an audio gadget, if the host starts transmitting on odd microframes.
This fix uses Incomplete Periodic
This patch allows the dwc3 driver to run on the new Synopsys USB 3.1
IP core, albeit in USB 3.0 mode only.
The Synopsys USB 3.1 IP (DWC_usb31) retains mostly the same register
interface and programming model as the existing USB 3.0 controller IP
(DWC_usb3). However, the underlying IP is different
Add platform data and set usb3_lpm_capable and has_lpm_erratum.
Cc: # v3.18+
Signed-off-by: John Youn
---
drivers/usb/dwc3/dwc3-pci.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-pci.c
This ID is for the Synopsys DWC_usb3 core with AXI interface on PCIe
HAPS platform. This core has the debug registers mapped at a separate
BAR in order to support enhanced hibernation.
Cc: # v3.18+
Signed-off-by: John Youn
---
Hi,
On Fri, Sep 04, 2015 at 07:15:10PM -0700, John Youn wrote:
> This patch allows the dwc3 driver to run on the new Synopsys USB 3.1
> IP core, albeit in USB 3.0 mode only.
>
> The Synopsys USB 3.1 IP (DWC_usb31) retains mostly the same register
> interface and programming model as the existing
On 10/1/2015 7:03 PM, Felipe Balbi wrote:
> Hi,
>
> On Fri, Sep 04, 2015 at 07:15:10PM -0700, John Youn wrote:
>> This patch allows the dwc3 driver to run on the new Synopsys USB 3.1
>> IP core, albeit in USB 3.0 mode only.
>>
>> The Synopsys USB 3.1 IP (DWC_usb31) retains mostly the same
Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
whether the PHY receives the suspend signal from the controller.
Certain Synopsys prototyping PHY boards are not able to meet timings
constraints for LPM. This allows the PHY to meet those timings by
leaving the PHY clock running
Hi,
This series contains several updates to dwc3 to support Synopsys
platforms.
Patch 1: Initial support for 3.1 IP (applies to all platforms)
Patch 2-4: PCI id and platform data for Synopsys platforms
Patch 5: Add a quirk to program a global register
Patch 6: Formatting
Thanks,
John
John Youn
This adds the PCI product ID for the Synopsys USB 3.1 IP core
(DWC_usb31) on a HAPS-based PCI development platform.
Cc: # v3.18+
Signed-off-by: John Youn
---
drivers/usb/dwc3/dwc3-pci.c | 5 +
1 file changed, 5 insertions(+)
diff --git
Fix the alignment of the PCI device definitions. Also change the hex
digit capitalization of one constant to make it consistent with the
rest of the file and driver.
Signed-off-by: John Youn
---
drivers/usb/dwc3/dwc3-pci.c | 16
1 file changed, 8
On Sat, Sep 26, 2015 at 12:31:08AM -0700, John Youn wrote:
> Add a quirk to clear the GUSB2PHYCFG.ENBLSLPM bit, which controls
> whether the PHY receives the suspend signal from the controller.
>
> Certain Synopsys prototyping PHY boards are not able to meet timings
> constraints for LPM. This
On Thu, Oct 01, 2015 at 12:29:32PM -0500, Felipe Balbi wrote:
> On Thu, Sep 24, 2015 at 10:39:23AM -0700, Baolin Wang wrote:
> > The usb charger framework is based on usb gadget. The usb charger
> > need to be notified the state changing of usb gadget to confirm the
> > usb charger state.
> >
> >
Hello,
Commit b0a688ddcc50 "usb: musb: cppi41: allow it to work again" seems
to fix a regression. It applies cleanly on v4.1 and removes the
"musb-hdrc musb-hdrc.1.auto: Need DT for the DMA engine." error.
Any chance you can queue it for -stable?
Thanks!
--
Ezequiel García, VanguardiaSur
Am Donnerstag, den 01.10.2015, 16:13 +0800 schrieb Peter Chen:
> On Wed, Sep 30, 2015 at 4:52 PM, Lucas Stach wrote:
> > Am Mittwoch, den 30.09.2015, 10:17 +0800 schrieb Peter Chen:
> >> It can improve the USB performance when choosing larger
> >> burst size at some
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