On Sun, Jun 26, 2016 at 12:28:30AM -0700, Stephen Boyd wrote:
> The chipidea core gets the usb phy and initializes the phy at the
> right point now so we don't need to get the phy in this driver.
>
> Cc: Peter Chen
> Cc: Greg Kroah-Hartman
> Signed-off-by: Stephen Boyd
> ---
> drivers/usb/chip
On Sun, Jun 26, 2016 at 12:28:29AM -0700, Stephen Boyd wrote:
> Sometimes the usb wrapper device is part of a power domain that
> needs to stay on as long as the device is active. Let's get and
> put the device in driver probe/remove so that we keep the power
> domain powered as long as the device
On Sun, Jun 26, 2016 at 12:28:28AM -0700, Stephen Boyd wrote:
> The MSM_USB_BASE macro trick is not very clear, and we're using
> it for only one register write so let's just move to using
> hw_write_id_reg() and passing the ci pointer instead. That
> clearly shows what offset we're using and avoid
On Sun, Jun 26, 2016 at 12:28:27AM -0700, Stephen Boyd wrote:
> The core framework already handles setting this parameter with a
> platform quirk. Add the appropriate flag so that we always set
> AHBBURST to 0. Technically DT should be doing this, but we always
> do it for msm chipidea devices so s
Hi,
Lee Jones writes:
> On the STiH410 B2120 development board the MiPHY28lp shares its reset
> line with the Synopsys DWC3 SuperSpeed (SS) USB 3.0 Dual-Role-Device
> (DRD). New functionality in the reset subsystems forces consumers to
> be explicit when requesting shared/exclusive reset lines.
On Sun, Jun 26, 2016 at 12:28:26AM -0700, Stephen Boyd wrote:
> Some phys for the chipidea controller are controlled via the ULPI
> viewport. Add support for the ULPI bus so that these sorts of
> phys can be probed and read/written automatically without having
> to duplicate the viewport logic in e
> From: Hayes Wang
> Sent: Tuesday, June 28, 2016 8:29 PM
> To: net...@vger.kernel.org
> Cc: nic_swsd; linux-ker...@vger.kernel.org; linux-usb@vger.kernel.org; Hayes
> Wang
> Subject: [PATCH net-next v3 0/7] r8152: support new chips
Excuse me. Please ignore these patches.
We want to do more tests
On Sun, Jun 26, 2016 at 12:28:25AM -0700, Stephen Boyd wrote:
> Force the OTG state machine to go forward when we're using an
> extcon for vbus detection. In this case, the controller may never
> raise an interrupt for AVVIS, so we need to simulate the event by
> toggling the appropriate OTG fsm bi
On Sun, Jun 26, 2016 at 12:28:23AM -0700, Stephen Boyd wrote:
> The ULPI phy on qcom platforms needs to be initialized and
> powered on after a USB reset and before we toggle the run/stop
> bit. Otherwise, the phy locks up and doesn't work properly.
This requirement is so strange, try to see if an
On Tue, Jun 28, 2016 at 02:42:05PM +0300, Heikki Krogerus wrote:
> On Mon, Jun 27, 2016 at 03:10:40PM -0700, Stephen Boyd wrote:
> > Quoting Heikki Krogerus (2016-06-27 07:34:22)
> > > Hi,
> > >
> > > I'm fine with most of the patch, except..
> > >
> > > On Sun, Jun 26, 2016 at 12:28:19AM -0700,
Dear Heiko,
On 06/29/2016 12:41 AM, Heiko Stuebner wrote:
Hi William,
Am Dienstag, 28. Juni 2016, 11:18:04 schrieb William Wu:
So about the usb3 controller clk management, I think it should contain
the following clk:
1. aclk_usb3otg1
2. aclk_usb3otg0
3. aclk_usb3_grf
correct, aclk_usb3otgX
Hello,
I'm currently having some difficulty with getting my Surface 3 device
to resume from the "freeze" PM state with USB devices. This device
uses an Intel Cherry Trail xHCI host, enumerated over PCI. (I am able
to resume with the device's hardware buttons, which are simply gpio
keys.) I experie
Quoting Neil Armstrong (2016-06-28 01:49:37)
> On 06/26/2016 09:28 AM, Stephen Boyd wrote:
> > + uphy->cal_sleep_clk = clk = devm_clk_get(&ulpi->dev, "cal_sleep");
> > + if (IS_ERR(clk))
> > + return PTR_ERR(clk);
>
> Hi Stephen,
>
> In the bindings the cal_sleep is marked opt
On Mon, Jun 27, 2016 at 09:09:19PM +0900, Yoshihiro Shimoda wrote:
> This patch uses devm_usb_get_phy_by_phandle() instead of usb_get_phy()
> for device tree environment. This change is not compabile with the
> previous code, but it is no problem because nobody calls usb_bind_phy()
> for this drive
On Sat, Jun 25, 2016 at 10:24:54PM -0700, Stephen Boyd wrote:
> This is a minimal driver to support bringing a usb4604 device
> from microchip out of reset and into hub mode. The usb4604 device
> is related to the usb3503 device, but it didn't seem close enough
> to warrant putting both into the sa
On Sun, Jun 26, 2016 at 12:28:19AM -0700, Stephen Boyd wrote:
> The qcom HSIC ulpi phy doesn't have any bits set in the vendor or
> product id ulpi registers. This makes it impossible to make a
> ulpi driver match against the id registers. Add support to
> discover the ulpi phys via DT to help alle
On Fri, Jun 24, 2016 at 03:51:18PM -0300, Bruno Herrera wrote:
> On Fri, Jun 24, 2016 at 12:41 PM, Rob Herring wrote:
> > On Tue, Jun 21, 2016 at 11:25:49PM -0300, Bruno Herrera wrote:
> >> Signed-off-by: Bruno Herrera
> >> ---
> >> Documentation/devicetree/bindings/usb/dwc2.txt | 1 +
> >> 1 fi
Interesting, thanks for the interpretation!
The device works correctly on another USB3 (front USB3, different
controller), so I'm not sure we can tell if there is an issue with the
device itself.
Unfortunately I do not have another USB3 device to test it. I'll try
to acquire one.
In the mean time,
Hi William,
Am Dienstag, 28. Juni 2016, 11:18:04 schrieb William Wu:
> >> So about the usb3 controller clk management, I think it should contain
> >> the following clk:
> >> 1. aclk_usb3otg1
> >> 2. aclk_usb3otg0
> >> 3. aclk_usb3_grf
> >
> > correct, aclk_usb3otgX would then be the busclk for
Am 2016-06-23 um 19:18 schrieb Dmitry Torokhov:
> Hi Martin,
>
> On Tue, Jun 14, 2016 at 01:20:15PM +0200, Martin Kepplinger wrote:
>> static int pegasus_reset_resume(struct usb_interface *intf)
>> {
>> +struct pegasus *pegasus = usb_get_intfdata(intf);
>> +
>> +if (pegasus->dev->users)
On 06/28/2016 11:40 AM, Alan Stern wrote:
> On Tue, 28 Jun 2016, Joseph Salisbury wrote:
>
>> On 06/24/2016 08:06 AM, Joseph Salisbury wrote:
>>> On 06/22/2016 12:14 PM, Greg KH wrote:
On Wed, Jun 22, 2016 at 11:38:43AM -0400, Joseph Salisbury wrote:
> Hi Rupesh,
>
> A kernel bug r
On Tue, 28 Jun 2016, Joseph Salisbury wrote:
> On 06/24/2016 08:06 AM, Joseph Salisbury wrote:
> > On 06/22/2016 12:14 PM, Greg KH wrote:
> >> On Wed, Jun 22, 2016 at 11:38:43AM -0400, Joseph Salisbury wrote:
> >>> Hi Rupesh,
> >>>
> >>> A kernel bug report was opened against Ubuntu [0]. After a
On 06/24/2016 08:06 AM, Joseph Salisbury wrote:
> On 06/22/2016 12:14 PM, Greg KH wrote:
>> On Wed, Jun 22, 2016 at 11:38:43AM -0400, Joseph Salisbury wrote:
>>> Hi Rupesh,
>>>
>>> A kernel bug report was opened against Ubuntu [0]. After a kernel
>>> bisect, it was found that reverting the followi
On 06/28/2016 06:12 AM, Heikki Krogerus wrote:
On Mon, Jun 27, 2016 at 06:39:46AM -0700, Guenter Roeck wrote:
On 06/27/2016 05:13 AM, Heikki Krogerus wrote:
Hi,
On Mon, Jun 27, 2016 at 03:51:08PM +0530, Rajaram R wrote:
May be I am missing user or usage of the driver.. I see this driver is
pr
On Mon, Jun 27, 2016 at 06:39:46AM -0700, Guenter Roeck wrote:
> On 06/27/2016 05:13 AM, Heikki Krogerus wrote:
> > Hi,
> >
> > On Mon, Jun 27, 2016 at 03:51:08PM +0530, Rajaram R wrote:
> > > May be I am missing user or usage of the driver.. I see this driver is
> > > providing limited informatio
v3:
Insert a patch "r8152: add u2p3_enable for rtl_ops".
Change the patch "r8152: support RTL8153B". Disable U2P3.
v2:
Fix the commit message for patch #6.
v1:
In order to support new chips, adjust some codes. Then, add the settings
for the new chips.
Hayes Wang (7):
r8152: add aldps_enable f
Add aldps_enable() for rtl_ops.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index 11178f9..b253003 100644
--- a/drivers/net/usb/r8152.c
+++ b/drive
Add u2p3_enable() for rtl_ops.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index a4f8a01..df370e5 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb
Support new chip RTL8153B.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 569 +---
1 file changed, 542 insertions(+), 27 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index 7227931..bd74fab 100644
--- a/drivers/
Add byte_enable for ocp_read_word() to replace reading 4
bytes data with reading the desired 2 bytes data.
This is used to avoid the issue which is described in
commit b4d99def0938 ("r8152: remove sram_read"). The
original method always reads 4 bytes data, and it may
have problem when reading the
Add u1u2_enable() for rtl_ops.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index b253003..f51d799 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/u
Add power_cut_en() for rtl_ops.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 16 +---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index f51d799..a4f8a01 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/
Support a new chip which has the product ID 0x8050.
Signed-off-by: Hayes Wang
---
drivers/net/usb/r8152.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index df370e5..7227931 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/u
On Mon, Jun 27, 2016 at 03:10:40PM -0700, Stephen Boyd wrote:
> Quoting Heikki Krogerus (2016-06-27 07:34:22)
> > Hi,
> >
> > I'm fine with most of the patch, except..
> >
> > On Sun, Jun 26, 2016 at 12:28:19AM -0700, Stephen Boyd wrote:
> > > @@ -39,7 +42,10 @@ static int ulpi_match(struct devic
On Sun, Jun 26, 2016 at 12:28:22AM -0700, Stephen Boyd wrote:
> We're currently emulating the vbus and id interrupts in the OTGSC
> read API, but we also need to make sure that if we're handling
> the events with extcon that we don't enable the interrupts for
> those events in the hardware. Therefo
On Mon, Jun 27, 2016 at 12:07:54PM -0700, Stephen Boyd wrote:
> Quoting Jun Li (2016-06-27 01:04:39)
> > > diff --git a/drivers/usb/chipidea/otg.c b/drivers/usb/chipidea/otg.c index
> > > 03b6743461d1..763a8332b009 100644
> > > --- a/drivers/usb/chipidea/otg.c
> > > +++ b/drivers/usb/chipidea/otg.c
On the STiH410 B2120 development board the MiPHY28lp shares its reset
line with the Synopsys DWC3 SuperSpeed (SS) USB 3.0 Dual-Role-Device
(DRD). New functionality in the reset subsystems forces consumers to
be explicit when requesting shared/exclusive reset lines.
Signed-off-by: Lee Jones
---
F
Philipp,
I need this to go into the -rcs too.
Can I add it with your Ack please?
> Consumers need to be able to specify whether they are requesting an
> 'exclusive' or 'shared' reset line no matter which API (of_*, devm_*,
> etc) they are using. This change allows users of the optional_* API
>
On 06/26/2016 09:28 AM, Stephen Boyd wrote:
> The HSIC USB controller on qcom SoCs has an integrated all
> digital phy controlled via the ULPI viewport.
>
> Cc: Kishon Vijay Abraham I
> Cc:
> Signed-off-by: Stephen Boyd
> ---
> .../devicetree/bindings/phy/qcom,usb-hsic-phy.txt | 60
Hi,
On 27-06-16 23:12, Alistair Buxton wrote:
I have a USB to SATA bridge which claims to be a ASM1153. It works
fine with all the other drives I tried, but not with a Crucial MX100
512GB SSD. I can read approximately the first 1.7GB of the disk with
dd and then it stops, always at the same poin
On Tue, 28 Jun 2016, Lee Jones wrote:
> On Mon, 06 Jun 2016, Alan Stern wrote:
>
> > On Mon, 6 Jun 2016, Lee Jones wrote:
> >
> > > On the STiH410 B2120 development board the ST EHCI IP shares its reset
> > > line with the OHCI IP. New functionality in the reset subsystems forces
> > > consumer
On Mon, 06 Jun 2016, Alan Stern wrote:
> On Mon, 6 Jun 2016, Lee Jones wrote:
>
> > On the STiH410 B2120 development board the ST EHCI IP shares its reset
> > line with the OHCI IP. New functionality in the reset subsystems forces
> > consumers to be explicit when requesting shared/exclusive res
On Tue, 07 Jun 2016, Kishon Vijay Abraham I wrote:
>
>
> On Monday 06 June 2016 09:26 PM, Lee Jones wrote:
> > On the STiH410 B2120 development board the MiPHY28lp shares its reset
> > line with the Synopsys DWC3 SuperSpeed (SS) USB 3.0 Dual-Role-Device
> > (DRD). New functionality in the reset
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