[linux-yocto] [yocto-4.12][PATCH 36/36] ALSA: hda/realtek - Fix ALC700 family no sound issue

From: Kailang Yang commit 2d7fe6185722b0817bb345f62ab06b76a7b26542 upstream. It maybe the typo for ALC700 support patch. To fix the bit value on this patch. Fixes: 6fbae35a3170 ("ALSA: hda/realtek - Add support for new codecs ALC700/ALC701/ALC703") Signed-off-by: Kailang

[linux-yocto] [yocto-4.12][PATCH 35/36] ALSA: hda - Add model string for Intel reference board quirk

From: Takashi Iwai commit 28d1d6d2f314ff395ff67565d1145742614b21c8 upstream. For allowing user to apply the existing quirk on a machine with a different SSID, add a new model string entry, alc700-ref. The quirk itself was introduced in the commit b84e843644f2: "ALSA: hda/realtek

[linux-yocto] [yocto-4.12][PATCH 33/36] ALSA: hda: Add Cannonlake PCI ID

From: Guneshwor Singh commit 2357f6f00098a437f9de084c3c34254d20dea789 upstream. Cannonlake is next generation Intel platform. This commit adds PCI ID for it. Signed-off-by: Guneshwor Singh Signed-off-by: Takashi Iwai

[linux-yocto] [yocto-4.12][PATCH 34/36] ALSA: hda/realtek - Enable jack detection function for Intel ALC700

From: PeiSen Hou commit b84e843644f211dbddcd65ba80732bdc3acf5380 upstream. Intel ALC 700 needs this patch for jack detection function. Because ALC700's jack detect function defaults is disable. So alc700 needs pathc to enable jack detection function. Signed-off-by: PeiSen

[linux-yocto] [yocto-4.12][PATCH 32/36] ALSA: hda - Fix unbalance of i915 module refcount

From: Takashi Iwai commit fc18282cdcba984ab89c74d7e844c10114ae0795 upstream. The commit dba9b7b6ca1a ("ALSA: hda - Fix doubly initialization of i915 component") contained a typo that leads to the unbalance of i915 module reference. The value to be checked is not

[linux-yocto] [yocto-4.12][PATCH 31/36] ALSA: hda - Fix doubly initialization of i915 component

From: Takashi Iwai commit dba9b7b6ca1af60fd21137c18795a81a5652c5ae upstream. In the commit fcc88d91cd36 ("ALSA: hda - Bind with i915 component before codec binding"), the binding with i915 audio component is moved to be performed always at probing the controller. This fixed the

[linux-yocto] [yocto-4.12][PATCH 28/36] drm/i915/cnl: Implement CNL display init/unit sequence

From: Ville Syrjälä commit d8d4a512a6ffa97bde442023e87b9c87a37d8838 upstream. Implement the CNL display init/uninit sequence as outlined in Bspec. Quite similar to SKL/BXT. The main complicaiton is probably the extra procmon setup we must do based on the

[linux-yocto] [yocto-4.12][PATCH 29/36] ALSA: hda - Add AZX_DRIVER_SKL for simplification

From: Takashi Iwai commit a4b4793f640b72af3e2bb2a1ad79725c103d5e40 upstream. We checked the quirks specific to the recent Intel chips by checking the PCI IDs manually, but it's becoming messy with lots of IS_SKL() and other macros, as the amount accumulated. For simplification,

[linux-yocto] [yocto-4.12][PATCH 26/36] drm/i915/cnl: Implement .get_display_clock_speed() for CNL

From: Ville Syrjälä commit 945f2672ccbb5c92a8a7bf23cba3a68a6b0885e7 upstream. Add support for reading out the cdclk frequency from the hardware on CNL. Very similar to BXT, with a few new twists and turns: * the PLL is now called CDCLK PLL, not DE PLL * reference

[linux-yocto] [yocto-4.12][PATCH 27/36] drm/i915/cnl: Implement .set_cdclk() for CNL

From: Ville Syrjälä commit ef4f7a689ac5f61e36ac9ae77ac967b6469ae68b upstream. Add support for changing the cdclk frequency on CNL. Again, quite similar to BXT, but there are some annoying differences which means trying to share more code might not be feasible: *

[linux-yocto] [yocto-4.12][PATCH 21/36] drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku.

From: Anusha Srivatsa commit ccfd13215fd25a0e8c28221f3acc0dcaec11cd15 upstream. Add PCI Ids for H Sku by following the BSpec. v2: Remove unused INTEL_CFL_IDS.(Rodrigo). v3: Add missing IDs(Rodrigo) Cc: Rodrigo Vivi Signed-off-by: Anusha

[linux-yocto] [yocto-4.12][PATCH 25/36] drm/i915/cfl: Coffee Lake reuses Kabylake DMC.

From: Rodrigo Vivi commit 84cd843e715298bbfb17ed40c7d61d7db6854a70 upstream. both platforms. We haven't recieved any separated release specifically for Coffee Lake so let's just re-use what is already there for Kabylake. Signed-off-by: Rodrigo Vivi

[linux-yocto] [yocto-4.12][PATCH 24/36] drm/i915/huc: Load HuC on Coffee Lake

From: Anusha Srivatsa commit 5e5d8b664effe57dc459e082fc37b1aec23f184a upstream. Coffee Lake reuses Kabylake's HUC firmware. v2: Change Coffeelake to Coffee Lake Cc: Rodrigo Vivi Signed-off-by: Anusha Srivatsa

[linux-yocto] [yocto-4.12][PATCH 19/36] drm/i915/cfl: Introduce Display workarounds for Coffee Lake.

From: Rodrigo Vivi commit 82525c17dedca6316b07c20c62627c83800caa31 upstream. The whole Display engine for Coffee Lake is pretty much identical to the Kabylake. For this reason let's reuse all display related production workardounds here even though CFL is not explicit

[linux-yocto] [yocto-4.12][PATCH 18/36] drm/i915/cfl: Coffee Lake uses CNP PCH.

From: Rodrigo Vivi commit 809378196bb449fe30d0ca15a990965fc553f9f5 upstream. So let's force it on the virtual detection. Also it is still the only silicon for now on this PCH, so WARN otherwise. v2: Rebased on top of Cannonlake and added the missed debug message as

[linux-yocto] [yocto-4.12][PATCH 22/36] drm/i915/cfl: Add Coffee Lake PCI IDs for U Sku.

From: Anusha Srivatsa commit d29fe702c9cb682df99146d24d06e5455f043101 upstream. Add PCI Ids for U Skus of Coffeelake. v2: Use intel_coffeelake_gt3_info, in accordance to- Rodrigo's patch: v3: rebased v3: Remove unused INTEL_CFL_IDS(Rodrigo). Cc: Rodrigo Vivi

[linux-yocto] [yocto-4.12][PATCH 20/36] drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus.

From: Anusha Srivatsa commit b056f8f3d6b900e8afd19f312719160346d263b4 upstream. Add PCI Ids for S Sku following the BSpec. v2: Remove the unused INTEL_CFL_IDS.(Rodrigo) v3: Add missing IDs(Rodrigo) Cc: Rodrigo Vivi Signed-off-by: Anusha

[linux-yocto] [yocto-4.12][PATCH 17/36] drm/i915/cfl: Introduce Coffee Lake platform definition.

From: Rodrigo Vivi commit 71851fa82f4d644f947dd60cfcf81b47640c1b51 upstream. Coffee Lake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen9 graphics based platform on top of CNP PCH. Let's start by adding the platform definition based on

[linux-yocto] [yocto-4.12][PATCH 15/36] drm/i915/cnl: Add power wells for CNL

From: Ville Syrjälä commit 8bcd3dd417660dce8cf38a731a888f09e8028190 upstream. CNL power wells are very similar to SKL, with the exception that the misc IO well has been split into separate AUX IO wells. Not sure if DMC is supposed to manage the AUX wells for us

[linux-yocto] [yocto-4.12][PATCH 11/36] drm/i915/cnl: add IS_CNL_REVID macro

From: Paulo Zanoni commit 3c2e0fd92c194f495aaa8a8a1c86ea1b8c4bd304 upstream. We're going to use it in the next commits. Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: Jim Bride

[linux-yocto] [yocto-4.12][PATCH 14/36] drm/i915/cnl: Cannonlake has same MOCS table than Skylake.

From: Rodrigo Vivi commit 1dc0766c33473d61fd85caa5031daf34f719cd3f upstream. All registers and default configuration are the same for Skylake and Cannonlake. v2: Don't apply Wa for platforms without MOCS. (Paulo) v3: Removed WaDisableSkipCaching that Joonas noticed

[linux-yocto] [yocto-4.12][PATCH 16/36] drm/i915/cnl: Also need power well sanitize.

From: Rodrigo Vivi commit bf9a496a1fa434670285bd592c75d009cbb99720 upstream. The workaround added in commit c6782b76d31a ("drm/i915/gen9: Reset secondary power well equests left on by DMC/KVMR") needs to be applied on Cannonlake as well. So let's assume any platform

[linux-yocto] [yocto-4.12][PATCH 07/36] drm/i915/cnl: Introduce Cannonlake platform defition.

From: Rodrigo Vivi commit 413f3c19f8ecefd29067897db9c414a29d86685f upstream. Cannonlake is a Intel® Processor containing Intel® HD Graphics following Kabylake. It is Gen10. Let's start by adding the platform definition based on previous platforms but yet as

[linux-yocto] [yocto-4.12][PATCH 13/36] drm/i915/cnl: Configure EU slice power gating.

From: Rodrigo Vivi commit c7ae7e9ab2078ed987903bc6c308abe57d575a59 upstream. Cannonlake also supports slice power gating on devices with more than one slice as SKL. Let's assume that this is the same for SKL+ and exclude BXT only. v2: Also remove KBL. Signed-off-by:

[linux-yocto] [yocto-4.12][PATCH 10/36] drm/i915/cnl: Add Cannonlake PCI IDs for Y-skus.

From: Rodrigo Vivi commit 95578277cbdb60e3c68cb92c843cafc1f77c4f55 upstream. By the Spec all CNL Y skus are 2+2, i.e. GT2. v2: Really include the PCI IDs to the picidlist[]; Reviewed-by: Anusha Srivatsa Signed-off-by: Rodrigo Vivi

[linux-yocto] [yocto-4.12][PATCH 12/36] drm/i915/cnl: Cannonlake has 4 planes (3 sprites) per pipe

From: James Irwin commit 8366be98f6792419ac2e19648391988edec7a7fe upstream. Issue: VIZ-4525 Reviewed-by: Damien Lespiau Signed-off-by: James Irwin Signed-off-by: Damien Lespiau Reviewed-by:

[linux-yocto] [yocto-4.12][PATCH 09/36] drm/i915/cnl: Add Cannonlake PCI IDs for U-skus.

From: Rodrigo Vivi commit e918d79a5d0a1b431e2cac0e6e6ac9452fd9ab32 upstream. Platform enabling and its power-on are organized in different skus (U x Y x S x H, etc). So instead of organizing it in GT1 x GT2 x GT3 let's also use the platform sku. This is also the new

[linux-yocto] [yocto-4.12][PATCH 08/36] drm/i915/cnl: Cannonlake uses CNP PCH.

From: Rodrigo Vivi commit acf1dba661e908e923320b4226bad4d8fc23c6f5 upstream. Avoid warning when CNP is detected with CNL. Also let's force it on the virtual detection. Signed-off-by: Rodrigo Vivi Reviewed-by: Anusha Srivatsa

[linux-yocto] [yocto-4.12][PATCH 03/36] drm/i915/cnp: Get/set proper Raw clock frequency on CNP.

From: Rodrigo Vivi commit 9d81a99713bc29b2f96403b8f7c1720e1b277b35 upstream. RAWCLK_FREQ register has changed for platforms with CNP+. [29:26] This field provides the denominator for the fractional part of the microsecond counter divider. The numerator

[linux-yocto] [yocto-4.12][PATCH 05/36] drm/i915/cnp: add CNP gmbus support

From: Rodrigo Vivi commit 3d02352cd9e8b43805bf68e50e395fda2e218791 upstream. On CNP PCH based platforms the gmbus is on the south display that is on PCH. The existing implementation for previous platforms already covers the need for CNP expect for the pin pair

[linux-yocto] [yocto-4.12][PATCH 04/36] drm/i915/cnp: Backlight support for CNP.

From: Rodrigo Vivi commit 4c9f7086ac6d069d5b79ba37ef4f1ed4fa3dc3f7 upstream. Split out BXT and CNP's setup_backlight(),enable_backlight(), disable_backlight() and hz_to_pwm() into two separate functions instead of reusing BXT function. Reuse set_backlight() and

[linux-yocto] [yocto-4.12][PATCH 06/36] drm/i915/cnp: Panel Power sequence changes for CNP PCH.

From: Rodrigo Vivi commit 938361e7a50619b76a1415c86438eaee41397220 upstream. Panel Power sequences for CNP is similar to Broxton, but with only one sequencer. Main difference from SPT is that PP_DIVISOR was removed and power cycle delay has been moved to PP_CONTROL.

[linux-yocto] [yocto-4.12][PATCH 02/36] drm/i915/cnp: Add PCI ID for Cannonpoint LP PCH

From: Dhinakaran Pandiyan commit ec7e0bb35f8d339b51b440b5fc525618784f11f4 upstream. The first two bytes of PCI ID for CNP_LP PCH are the same as that of SPT_LP. We should really be looking at the first 9 bits instead of the first 8 to identify platforms, although

[linux-yocto] [yocto-4.12][PATCH 01/36] drm/i915/cnp: Introduce Cannonpoint PCH.

From: Rodrigo Vivi commit 7b22b8c402c8ee26dd4dc1474887a2a91961e766 upstream. Most of south engine display that is in PCH is still the same as SPT and KBP, except for this key differences: - Backlight: Backlight programming changed in CNP PCH. - Panel Power: Sligh

[linux-yocto] [yocto-4.12][PATCH 00/36] add graphic and audio support for CFL-S

These 36 upstream patches use to enable graphic and audio support for CoffeeLake-s board. Some cnl patches were backported due to dependency. Anusha Srivatsa (5): drm/i915/cfl: Add Coffee Lake PCI IDs for S Skus. drm/i915/cfl: Add Coffee Lake PCI IDs for H Sku. drm/i915/cfl: Add Coffee

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

On 2018年01月10日 11:11, Bruce Ashfield wrote: On 2018-01-09 9:07 PM, qwang2 wrote: Hi Bruce, This commit is based on the patches at https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html. It seems that those patches hasn't been merged, would you please help to check it?

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

On 2018-01-09 9:07 PM, qwang2 wrote: Hi Bruce, This commit is based on the patches at https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html. It seems that those patches hasn't been merged, would you please help to check it? Send them all in a completes series. What I

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

Hi Bruce, This commit is based on the patches at https://www.mail-archive.com/linux-yocto@yoctoproject.org/msg06131.html. It seems that those patches hasn't been merged, would you please help to check it? Thanks, Quanyang On 2018年01月10日 02:19, Bruce Ashfield wrote: This series doesn't

Re: [linux-yocto] [yocto-4.12][PATCH 1/3] x86/intel_rdt: Move special case code for Haswell to a quirk function

This series doesn't apply to the current 4.12: - Applying: x86/intel_rdt: Move special case code for Haswell to a quirk function error: patch failed: arch/x86/kernel/cpu/intel_rdt.c:172 error: arch/x86/kernel/cpu/intel_rdt.c: patch does not apply Patch failed at 0001

Re: [linux-yocto] [yocto-4.12] [PATCH] kvm : enable VHOST of host for qemu running guest

this has now been staged and pushed to the yocto kernel cache repo. Bruce On 01/04/2018 04:53 AM, Hongzhi.Song wrote: Signed-off-by: Hongzhi.Song --- features/kvm/qemu-kvm.cfg | 9 + 1 file changed, 9 insertions(+) diff --git a/features/kvm/qemu-kvm.cfg