From: Ong Boon Leong boon.leong@intel.com
This patch is for Linux v3.10 meta:
- to change default NR_CPUS from 8 to 24. This is required
to ensure Romley platform which has 24 processors are all
activated by default when intel-common image is booted.
The above changes have been build-
From: Ong Boon Leong boon.leong@intel.com
This patch is for Linux v3.10 meta:
- to change default NR_CPUS from 8 to 64. This is required
to ensure platform which has more than 8 processors are all
activated by default when intel-common image is booted.
The above changes have been build-
From: Ong Boon Leong boon.leong@intel.com
Change CONFIG_NR_CPUS from 8 to 64 so that platform with
processors count more than 8 will be all activited.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
meta/cfg/kernel-cache/cfg/smp.cfg |3 +++
1 file changed, 3 insertions(+)
From: Ong Boon Leong boon.leong@intel.com
Changed intel-corei7064-preempt-rt-scc file name to
intel-corei7-64-preempt-rt.scc.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
.../{intel-corei7064-preempt-rt-scc = intel-corei7-64-preempt-rt.scc} |0
1 file changed, 0
From: Ong Boon Leong boon.leong@intel.com
This patchset contains fixes for the following:
1) fix to incorrect filename in bsp/intel-common/
intel-corei7064-preempt-rt-scc.
2) remove mohonpeak branch from bsp/mohonpeak/
mohonpeak-standard.scc. It uses standard/base now.
In addition,
From: Ong Boon Leong boon.leong@intel.com
This is to remove 'mohonpeak' branch from scc file since
we are migrating the BSP to use intel-common.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
meta/cfg/kernel-cache/bsp/mohonpeak/mohonpeak-standard.scc |3 +--
From: Ong Boon Leong boon.leong@intel.com
This patch is to add mohonpeak 32-bit 64-bit BSP support
into intel-common BSP recipe.
Please pull this patch into linux-yocto v3.10 meta branch.
Thank you very much
Ong Boon Leong
The following changes since commit
From: Ong Boon Leong boon.leong@intel.com
Update mohonpeak.cfg to enable SMBus iSMT driver, crypto framework,
LPC, watchdog-timer 4G memory for 32-bit build. The update is possible
due to recent merge of LTS/LTSI commits available since 3.4.74.
Remove CONFIG_PATA_SCH because pata_sch.c
From: Ong Boon Leong boon.leong@intel.com
Changelog:
Update commit header to explain why PATA_SCH config is removed and
SATA_AHCI config is enabled.
This patch is meant to update mohonpeak.cfg to include new features
made possible by recent merge on linux-yocto v3.4 since LTSI/LTS v3.4.74.
From: Ong Boon Leong boon.leong@intel.com
This patch is meant to update mohonpeak.cfg to include new features
made possible by recent merge on linux-yocto v3.4 since LTSI/LTS v3.4.74.
I have done build-test and image-test on the cfg changes and found fit.
Please kindly review and if the
From: Ong Boon Leong boon.leong@intel.com
Update mohonpeak.cfg to enable SMBus iSMT driver, crypto framework,
LPC, watchdog-timer 4G memory for 32-bit build. The update is possible
due to recent merge of LTS/LTSI commits available since 3.4.74.
Signed-off-by: Ong Boon Leong
From: Ong Boon Leong boon.leong@intel.com
The requested GPIO pin must has the function mux bits set
to GPIO function by BIOS in advance. Else, the gpio pin
request would fail. This is to ensure that we do not expose
any GPIO pins which shall be used for other purposes,
for eg: wakeup pin, I/O
From: Ong Boon Leong boon.leong@intel.com
This is to cater the need for non-ACPI system whereby
a platform device has to be created in order to bind
with the BYT GPIO platform driver.
This commit is only applicable for v3.8 GPIO driver and not after.
For v3.10 onwards, only ACPI enumeration
From: Ong Boon Leong boon.leong@intel.com
In to_irq() callback, we create the hwirq to linux irq
mapping for the requested GPIO pin. Hence, we unamp
the mapping when the gpio pin is being released.
This commit is only applicable for v3.8 GPIO driver and not after.
For v3.10 onwards, as of
From: Ong Boon Leong boon.leong@intel.com
This patchset is to enable Intel BayTrail GPIO driver.
For background of the development, the base of GPIO driver is
developed by Mathias Nyman before the driver is migrated
to pinctrl model post v3.8.
To avoid pulling in the complexity involved in
From: Ong Boon Leong boon.leong@intel.com
Add gpio support for Intel BayTrail PCH chipset. BayTrail supports 3 banks
of gpios called SCORE, NCORE ans SUS with 102, 28 and 44 gpio pins.
Updated with commit changes in upstream on pinctrl driver.
This gpio driver is only applicable for v3.8
From: Ong Boon Leong boon.leong@intel.com
Update configs used in the latest GPIO feature patch series.
Add the list of patch series into valleyisland-io.scc.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
.../kernel-cache/features/valleyisland-io/valleyisland-io-pci.cfg |2
From: Ong Boon Leong boon.leong@intel.com
SD Card v3.01 in the market is not compatible with BYT SDHC IP
in SoC because this IP only support SD v3.0 only. So, we are
forcing DDR50 mode to always step down to SDR25.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
From: Ong Boon Leong boon.leong@intel.com
add PCI ID of Intel BayTrail SMBus controller.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
.../0015-i2c-i801-Enable-BYT-SMBUS-support.patch | 35
1 file changed, 35 insertions(+)
create mode 100644
From: Ong Boon Leong boon.leong@intel.com
This is the PCI part of the DesignWare DMAC driver.
The controller is usually used in the Intel hardware such as Medfield.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
...engine-dw_dmac-add-PCI-part-of-the-driver.patch | 198
From: Ong Boon Leong boon.leong@intel.com
Instead of always depending on formula to calculate the HCNT and LCNT set
the HCNT, LCNT and SDA if the target values are known beforehand.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
...are-pcidrv-Option-to-set-custom-HCNT-LCNT.patch
From: Ong Boon Leong boon.leong@intel.com
This improves the accuracy of base_unit calculation
so that the resulting PWM frequency will be more optimal.
The change in the patch is meant for Intel BayTrail only
because pwm-lpss.c is only used for this platform.
Signed-off-by: Ong Boon Leong
From: Ong Boon Leong boon.leong@intel.com
this commit enables the following:
- setup clock tree for PCI mode SPI, DMA and PWM host
as the controller drivers require clock information during
device/driver probe
- register SPI slave
Signed-off-by: Ong Boon Leong
From: Ong Boon Leong boon.leong@intel.com
This is to enable PCI mode of Intel BayTrail LPSS I2C.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
...are-pci-Add-support-for-Intel-BayTrail-LP.patch | 125
1 file changed, 125 insertions(+)
create mode 100644
From: Ong Boon Leong boon.leong@intel.com
Intel BayTrail LPSS includes two PWM controllers which can be
enumerated from ACPI namespace.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
.../0008-ACPI-LPSS-Add-BYT-ACPI-mode-PWM.patch | 45
1 file changed,
From: Ong Boon Leong boon.leong@intel.com
For Intel BayTrail, enable i2c-designware-pci host controller
to support 10-bit addressing mode functionality.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
...are-pcidrv-Add-10-bit-addressing-mode-fun.patch | 114
From: Ong Boon Leong boon.leong@intel.com
To create Haswell Platform (Walnut Canyon CRB) cfg scc files
for linux-yocto_3.10 meta branch.
Signed-off-by: Ong Boon Leong boon.leong@intel.com
---
.../bsp/haswell-wc/haswell-wc-preempt-rt.scc | 15
From: Ong Boon Leong boon.leong@intel.com
To create Haswell Platform (Walnut Canyon CRB) cfg scc files under meta branch
Signed-off-by Ong Boon Leong boon.leong@intel.com
---
.../bsp/haswell-wc/haswell-wc-preempt-rt.scc | 15
From: Ong Boon Leong boon.leong@intel.com
To create mohonpeak its associated scc cfg files under meta branch
Signed-off-by Ong Boon Leong boon.leong@intel.com
---
.../bsp/mohonpeak/mohonpeak-preempt-rt.scc | 17 +
.../bsp/mohonpeak/mohonpeak-standard.scc
From: Ong Boon Leong boon.leong@intel.com
This commit is meant to add mohonpeak bsp under meta/cfg/kernel-cache/bsp.
Rangeley Program has decided to change its bsp name from rangeley to
mohonpeak in linux-yocto-3.4 meta branch.
So, can the maintainer for this git help to remove rangeley
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