From: Ong Boon Leong <boon.leong....@intel.com> This is to enable PCI mode of Intel BayTrail LPSS I2C.
Signed-off-by: Ong Boon Leong <boon.leong....@intel.com> --- ...are-pci-Add-support-for-Intel-BayTrail-LP.patch | 125 ++++++++++++++++++++ 1 file changed, 125 insertions(+) create mode 100644 meta/cfg/kernel-cache/features/valleyisland-io/0010-i2c-designware-pci-Add-support-for-Intel-BayTrail-LP.patch diff --git a/meta/cfg/kernel-cache/features/valleyisland-io/0010-i2c-designware-pci-Add-support-for-Intel-BayTrail-LP.patch b/meta/cfg/kernel-cache/features/valleyisland-io/0010-i2c-designware-pci-Add-support-for-Intel-BayTrail-LP.patch new file mode 100644 index 0000000..6972db7 --- /dev/null +++ b/meta/cfg/kernel-cache/features/valleyisland-io/0010-i2c-designware-pci-Add-support-for-Intel-BayTrail-LP.patch @@ -0,0 +1,125 @@ +From 0a68b53ed89babf66c938ae85a0b903128183178 Mon Sep 17 00:00:00 2001 +From: Kweh, Hock Leong <hock.leong.k...@intel.com> +Date: Mon, 13 Jan 2014 05:35:06 +0800 +Subject: [PATCH 10/17] i2c: designware-pci: Add support for Intel BayTrail + LPSS I2C + +This is to enable PCI mode of Intel BayTrail LPSS I2C. + +Signed-off-by: Kweh, Hock Leong <hock.leong.k...@intel.com> +--- + drivers/i2c/busses/i2c-designware-pcidrv.c | 70 +++++++++++++++++++++++++++- + 1 files changed, 69 insertions(+), 1 deletions(-) + +diff --git a/drivers/i2c/busses/i2c-designware-pcidrv.c b/drivers/i2c/busses/i2c-designware-pcidrv.c +index f6ed06c..afd8ae0 100644 +--- a/drivers/i2c/busses/i2c-designware-pcidrv.c ++++ b/drivers/i2c/busses/i2c-designware-pcidrv.c +@@ -54,6 +54,14 @@ enum dw_pci_ctl_id_t { + medfield_3, + medfield_4, + medfield_5, ++ ++ byt_0, ++ byt_1, ++ byt_2, ++ byt_3, ++ byt_4, ++ byt_5, ++ byt_6, + }; + + struct dw_pci_controller { +@@ -68,6 +76,10 @@ struct dw_pci_controller { + DW_IC_CON_SLAVE_DISABLE | \ + DW_IC_CON_RESTART_EN) + ++#define INTEL_BYT_STD_CFG (DW_IC_CON_MASTER | \ ++ DW_IC_CON_SLAVE_DISABLE | \ ++ DW_IC_CON_RESTART_EN) ++ + static struct dw_pci_controller dw_pci_controllers[] = { + [moorestown_0] = { + .bus_num = 0, +@@ -132,6 +144,55 @@ static struct dw_pci_controller dw_pci_controllers[] = { + .rx_fifo_depth = 32, + .clk_khz = 25000, + }, ++ [byt_0] = { ++ .bus_num = 0, ++ .bus_cfg = INTEL_BYT_STD_CFG | DW_IC_CON_SPEED_FAST, ++ .tx_fifo_depth = 32, ++ .rx_fifo_depth = 32, ++ .clk_khz = 100000, ++ }, ++ [byt_1] = { ++ .bus_num = 1, ++ .bus_cfg = INTEL_BYT_STD_CFG | DW_IC_CON_SPEED_FAST, ++ .tx_fifo_depth = 32, ++ .rx_fifo_depth = 32, ++ .clk_khz = 100000, ++ }, ++ [byt_2] = { ++ .bus_num = 2, ++ .bus_cfg = INTEL_BYT_STD_CFG | DW_IC_CON_SPEED_FAST, ++ .tx_fifo_depth = 32, ++ .rx_fifo_depth = 32, ++ .clk_khz = 100000, ++ }, ++ [byt_3] = { ++ .bus_num = 3, ++ .bus_cfg = INTEL_BYT_STD_CFG | DW_IC_CON_SPEED_FAST, ++ .tx_fifo_depth = 32, ++ .rx_fifo_depth = 32, ++ .clk_khz = 100000, ++ }, ++ [byt_4] = { ++ .bus_num = 4, ++ .bus_cfg = INTEL_BYT_STD_CFG | DW_IC_CON_SPEED_FAST, ++ .tx_fifo_depth = 32, ++ .rx_fifo_depth = 32, ++ .clk_khz = 100000, ++ }, ++ [byt_5] = { ++ .bus_num = 5, ++ .bus_cfg = INTEL_BYT_STD_CFG | DW_IC_CON_SPEED_FAST, ++ .tx_fifo_depth = 32, ++ .rx_fifo_depth = 32, ++ .clk_khz = 100000, ++ }, ++ [byt_6] = { ++ .bus_num = 6, ++ .bus_cfg = INTEL_BYT_STD_CFG | DW_IC_CON_SPEED_FAST, ++ .tx_fifo_depth = 32, ++ .rx_fifo_depth = 32, ++ .clk_khz = 100000, ++ }, + }; + static struct i2c_algorithm i2c_dw_algo = { + .master_xfer = i2c_dw_xfer, +@@ -254,7 +315,6 @@ static int i2c_dw_pci_probe(struct pci_dev *pdev, + I2C_FUNC_SMBUS_WORD_DATA | + I2C_FUNC_SMBUS_I2C_BLOCK; + dev->master_cfg = controller->bus_cfg; +- + pci_set_drvdata(pdev, dev); + + dev->tx_fifo_depth = controller->tx_fifo_depth; +@@ -321,6 +381,14 @@ static DEFINE_PCI_DEVICE_TABLE(i2_designware_pci_ids) = { + { PCI_VDEVICE(INTEL, 0x082C), medfield_0 }, + { PCI_VDEVICE(INTEL, 0x082D), medfield_1 }, + { PCI_VDEVICE(INTEL, 0x082E), medfield_2 }, ++ /* BYT */ ++ { PCI_VDEVICE(INTEL, 0x0F41), byt_0 }, ++ { PCI_VDEVICE(INTEL, 0x0F42), byt_1 }, ++ { PCI_VDEVICE(INTEL, 0x0F43), byt_2 }, ++ { PCI_VDEVICE(INTEL, 0x0F44), byt_3 }, ++ { PCI_VDEVICE(INTEL, 0x0F45), byt_4 }, ++ { PCI_VDEVICE(INTEL, 0x0F46), byt_5 }, ++ { PCI_VDEVICE(INTEL, 0x0F47), byt_6 }, + { 0,} + }; + MODULE_DEVICE_TABLE(pci, i2_designware_pci_ids); +-- +1.7.4.4 + -- 1.7.10.4 _______________________________________________ linux-yocto mailing list linux-yocto@yoctoproject.org https://lists.yoctoproject.org/listinfo/linux-yocto