On 2/10/14, 5:08, rebecca.swee.fun.ch...@intel.com
rebecca.swee.fun.ch...@intel.com wrote:
From: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Remove PCI mode LPSS deivce configurations. These
configurations are moved into a patch in recipe layer
in order for Valley Island LPSS
From: Chang, Rebecca Swee Fun rebecca.swee.fun.ch...@intel.com
Remove PCI mode LPSS deivce configurations. These
configurations are moved into a patch in recipe layer
in order for Valley Island LPSS devices to support both
ACPI mode and PCI mode enumeration.
Signed-off-by: Chang, Rebecca Swee
