Title: RE: ADLO for EPIA
Thanks.
It works and I can see something (just splash of colors) on my CRT.
The screen, though it is not usable, is brought up by original VGABIOS using ADLO.
Heechul.
> -Original Message-
> From: Andrew Ip [mailto:[EMAIL PROTECTED]]
> Sent: Monday, Ma
Hello Steve,
Monday, March 17, 2003, 4:56:02 AM, you wrote:
SG> Spirit wrote:
>> I've been reading the SIS630 datasheet and found out that the
>> chipset has a watchdog timer (for some reason they call it
>> 'software') similar to that of the i810.
>>
>> Does anybody here know if there i
On 17 Mar 2003, Eric W. Biederman wrote:
> As it stands right now I am in inch from moving the decompresser
> from code that runs from ROM to code that runs from RAM, to see if
> that fixes the performance issue.
didn't we make ROM cacheable yet? Rather than keep moving things to RAM,
if we make
Ronald G. Minnich wrote:
On Mon, 17 Mar 2003, Spirit wrote:
That shouldn't be a problem unless it takes 5 seconds to get to the
southbridge.c code. But of course, moving it to an earlier position is
a good idea.
It really takes 5 seconds? it did not used to. I liked having it in the
southbridg
Shubhangi Jadhav wrote:
how does crt0.base move to c_start.S. I did not find any reference to
c_start.S from crt0.base or any other .inc files included in crt0.base
The bottom of crt0.base jumps to c_start.S using loader "magic".
c_start.S runs in ram in the C code address space. crt0.base runs i
On Mon, 2003-03-17 at 21:35, Spirit wrote:
>
> What I would really like to see somewhere in the LinuxBIOS code is the
> options to disable SiS630 embedded modem and audio controllers. I
> browser through the datasheet and didn't find how to disable them. I
> probably should re-read it, but if any
"Ronald G. Minnich" <[EMAIL PROTECTED]> writes:
> On 17 Mar 2003, Eric W. Biederman wrote:
>
> > As it stands right now I am in inch from moving the decompresser
> > from code that runs from ROM to code that runs from RAM, to see if
> > that fixes the performance issue.
>
> didn't we make ROM ca
Eric W. Biederman wrote:
Steve Gehlbach <[EMAIL PROTECTED]> writes:
Ronald G. Minnich wrote:
How about using XIP_ROM_SIZE and XIP_ROM_BASE; seems to setup WP caching on
variable MTRR 0x203 (mem type=5). Or does this have other effects; maybe use a
different option with same code?
XIP is short
Steve Gehlbach <[EMAIL PROTECTED]> writes:
> Eric W. Biederman wrote:
> > Steve Gehlbach <[EMAIL PROTECTED]> writes:
> >
> >>Ronald G. Minnich wrote:
> >>How about using XIP_ROM_SIZE and XIP_ROM_BASE; seems to setup WP caching on
> >>variable MTRR 0x203 (mem type=5). Or does this have other effec
Eric W. Biederman wrote:
Error. Communications failure.
I meant this situation is exactly what it is designed for.
Sorry. I misunderstood.
I am also assuming the Via C3 has the variable MTRRs, that may not be a correct
assumption. The Intel book says P6 family.
Very good question what does
Steve Gehlbach <[EMAIL PROTECTED]> writes:
> Eric W. Biederman wrote:
>
> > Error. Communications failure.
> > I meant this situation is exactly what it is designed for.
>
> Sorry. I misunderstood.
>
> >
> >>I am also assuming the Via C3 has the variable MTRRs, that may not be a
> correct
>
On Mon, 17 Mar 2003, Spirit wrote:
> That shouldn't be a problem unless it takes 5 seconds to get to the
> southbridge.c code. But of course, moving it to an earlier position is
> a good idea.
It really takes 5 seconds? it did not used to. I liked having it in the
southbridge code for a simple r
"Ronald G. Minnich" <[EMAIL PROTECTED]> writes:
> On Mon, 17 Mar 2003, Spirit wrote:
>
> > That shouldn't be a problem unless it takes 5 seconds to get to the
> > southbridge.c code. But of course, moving it to an earlier position is
> > a good idea.
>
> It really takes 5 seconds? it did not use
On Mon, 17 Mar 2003, Steve Gehlbach wrote:
> Maybe it is related to running at 0x instead of 0xf. Did we
> cached that region? The mtrr code is there but I have not checked
> through it to see what regions are cached.
I am almost certain we do not cache that region. That might be
Ronald G. Minnich wrote:
On Mon, 17 Mar 2003, Steve Gehlbach wrote:
Maybe it is related to running at 0x instead of 0xf. Did we
cached that region? The mtrr code is there but I have not checked
through it to see what regions are cached.
I am almost certain we do not cache that r
Steve Gehlbach <[EMAIL PROTECTED]> writes:
> Ronald G. Minnich wrote:
> > On Mon, 17 Mar 2003, Steve Gehlbach wrote:
> >
> >> Maybe it is related to running at 0x instead of 0xf. Did we
> >> cached that region? The mtrr code is there but I have not checked through it
>
> >> to see w
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