* Uwe Hermann [EMAIL PROTECTED] [070528 02:40]:
Lower the RAM init delays we use on the Intel 440BX.
As per JEDEC, we should wait 200us until voltages and clocks are stable.
Then apply NOPs for 200 clock cycles (for simplicity we use 200us here).
All other delays are so low that we get
On Mon, May 28, 2007 at 02:40:10AM +0200, Uwe Hermann wrote:
Lower the RAM init delays we use on the Intel 440BX.
If it works,
Acked-by: Peter Stuge [EMAIL PROTECTED]
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Hi Uwe,
On Sunday 27 May 2007 22:59, Uwe Hermann wrote:
On Sun, May 27, 2007 at 07:19:18PM +0200, Juergen Beisert wrote:
Hi,
find below my CAR implementation for the Geode GX1 processor. Tested on
my Geode GX1 system. Comments are welcome.
Great, thanks!
Is this for v2 or v3 (or
So I testet a Epia CL with the Epia M file, as payload etherboot.
Output:
0
LinuxBIOS-2.0.0.0-Fallback Mon May 28 08:12:52 UTC 2007 starting...
Enabling mainboard devices
Enabling shadow ram
vt8623 init starting
nothing more
The interessting thing is that the Flashrom tool dedectet a Epia
Author: uwe
Date: 2007-05-28 16:34:05 +0200 (Mon, 28 May 2007)
New Revision: 338
Added:
LinuxBIOSv3/lib/ram.c
Log:
Initial version of a generic RAM initialization framework.
Signed-off-by: Ronald G. Minnich [EMAIL PROTECTED]
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
Acked-by: Peter Stuge
Author: uwe
Date: 2007-05-28 16:37:06 +0200 (Mon, 28 May 2007)
New Revision: 2702
Modified:
trunk/LinuxBIOSv2/src/northbridge/intel/i440bx/raminit.c
Log:
Lower the RAM init delays we use on the Intel 440BX.
As per JEDEC, we should wait 200us until voltages and clocks are stable.
Then apply
* Markus Boas [EMAIL PROTECTED] [070528 10:30]:
So I testet a Epia CL with the Epia M file, as payload etherboot.
What's the northbridge of the Epia CL?
run as root:
lspci -nnvvv
lspci -xxx
lspci -t
Best regards
Stefan
--
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
On Mon, May 28, 2007 at 04:32:33PM +0200, Peter Stuge wrote:
On Mon, May 28, 2007 at 10:30:53AM +0200, Markus Boas wrote:
The interessting thing is that the Flashrom tool dedectet a
Epia M/MII Board
flashrom can only guess, unfortunately. The heuristics used are
quite broad in some
Hi,
On Tue, May 22, 2007 at 03:14:42PM +0100, Ceri Coburn wrote:
I wanted to limit the number of temp's used as I didn't want ROMCC
complaining about no more registers available.
I was seeing the same problem when I tried to integrate your patch --
romcc runs out of registers.
The method
Am Montag 28 Mai 2007 schrieb Luc Verhaegen:
On Mon, May 28, 2007 at 04:32:33PM +0200, Peter Stuge wrote:
On Mon, May 28, 2007 at 10:30:53AM +0200, Markus Boas wrote:
The interessting thing is that the Flashrom tool dedectet a
Epia M/MII Board
flashrom can only guess, unfortunately.
Am Montag 28 Mai 2007 schrieb Stefan Reinauer:
* Markus Boas [EMAIL PROTECTED] [070528 10:30]:
So I testet a Epia CL with the Epia M file, as payload etherboot.
What's the northbridge of the Epia CL?
lspci -nnvvv
00:00.0 Host bridge [0600]: VIA Technologies, Inc. VT8623 [Apollo CLE266]
Hi,
btw, I've updated the list of potential recent mainboards which should
be relatively easy to support, see http://linuxbios.org/Desktops.
If anybody owns such a board or wants to work on a port, please let us
know!
Uwe.
--
http://www.hermann-uwe.de | http://www.holsham-traders.de
* Uwe Hermann [EMAIL PROTECTED] [070528 17:58]:
This patch works for me. It's strange that abuild doen't complain
here, but manually building does indeed not work...
Not at all. abuild only uses the Config.abuild template if it exists.
If not, it creates its own Config.lb with size 0x17000.
v3
Hi,
On Mon, May 28, Uwe Hermann wrote:
Try setting ROM_SIZE in the mainboard Config.lb to your rom size (512k?)
and ROM_IMAGE_SIZE in the targets/ Config.lb to 0x16000 or 0x17000
instead of 0x1 or whatever it is.
This patch works for me. It's strange that abuild doen't complain
On 5/22/07, Ceri Coburn [EMAIL PROTECTED] wrote:
I wanted to limit the number of temp's used as I didn't want ROMCC
complaining about no more registers available.
romcc is usually not that simple-minded, it should know about reuse.
Has too many temps
caused trouble for you?
I have tested
The ADL855PC uses an intel northbridge. Intel's stated policy, going
back some years now, is that they do not publish or make available the
info needed to write a bios. Period. To really get this to work, you
will have to contact intel for docs, and I hope they are willing to
help you. Maybe their
Hi,
On Sun, May 20, Dieter Bloms wrote:
On Sun, May 20, Uwe Hermann wrote:
(btw: patch is untested, of course)
the patch does the trick.
today I wrote an image to flash and it doesn't work.
There is allways the original image booting.
Here the output:
--snip--
Hi Dieter, your problem is indicative of one of several possible issues.
IIRC this part is one of those combined FWH/LPC parts. Can you verify
this on a data sheet?
Can you see if it is configured as LPC or FWH? I just had a real
problem with one of these.
I can't look in too much detail, right
Hi Ron,
On Mon, May 28, ron minnich wrote:
IIRC this part is one of those combined FWH/LPC parts. Can you verify
this on a data sheet?
yes, in the manual I can read RD1-PMC4 32pin PMC (FWH/LPC)
Can you see if it is configured as LPC or FWH? I just had a real
problem with one of these.
I
I have a question about Config.lb that I hope someone can help me with.
This is in order to get ACPI working on the EPIA board.
Ok in the mainboard Config.lb as part of the southbridge there is the
following line.
device pci 11.0 on # Southbrdge
:
:
device pnp 2e.a
Uwe Hermann wrote:
Hi,
On Tue, May 22, 2007 at 03:14:42PM +0100, Ceri Coburn wrote:
I wanted to limit the number of temp's used as I didn't want ROMCC
complaining about no more registers available.
I was seeing the same problem when I tried to integrate your patch --
romcc runs
ron minnich wrote:
On 5/22/07, Ceri Coburn [EMAIL PROTECTED] wrote:
I wanted to limit the number of temp's used as I didn't want ROMCC
complaining about no more registers available.
romcc is usually not that simple-minded, it should know about reuse.
Has too many temps
caused trouble for
S1832DL boot
session log:
http://www.eskimo.com/~roger/programming/linuxbios/index.html
http://www.eskimo.com/~roger/files/linuxbios/440BX.S1832DL/session-20070528.log
--
Roger
http://www.eskimo.com/~roger/index.html
Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61
Mon May 28
On Mon, 2007-05-28 at 23:24 -0400, Corey Osgood wrote:
On Mon, 2007-05-28 at 14:56 -0700, roger wrote:
On a side note, I'm having to use your tyan/s1846 profile instead of the
asus/p2b profile (after patching it with my superio) because I think the
asus/p2b/auto.c is buggy (... think Corey
The static device tree of the Tyan S1846 was, um... totally bogus.
I'm using the ide0_enble/ide1_enable variables now to enable IDE.
Hm, what happens if those variables are not set at all in a Confib.lb
file of some mainboard? Do they default to zero?
Uwe.
--
http://www.hermann-uwe.de |
On Tue, 2007-05-29 at 06:46 +0200, Uwe Hermann wrote:
Hi,
On Mon, May 28, 2007 at 08:20:30PM -0700, roger wrote:
It lives! ... well, until the kernel gets to init. The kernel usually
states my root partition is /dev/sda2 because of the usual add-in SATA
pci card. However, Filo
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