Hello!
I hope I'm not too far off the mark, and this is semi-offtopic, but what
I'm wondering about is udev and compact flash.
What I'm doing is installing Debian with FAI[1] and afterwards would be
flashing the bios with LinuxBios. The FAI installation works on a regular
hard drive just
On Mon, 17 Sep 2007, Markus Tornqvist wrote:
Hello!
I hope I'm not too far off the mark, and this is semi-offtopic, but what
I'm wondering about is udev and compact flash.
What I'm doing is installing Debian with FAI[1] and afterwards would be
flashing the bios with LinuxBios. The FAI
On Mon, Sep 17, 2007 at 12:28:42AM -0700, Russell Whitaker wrote:
The problem: I'm not seeing the cflash /dev/hde. It's found a-ok by
lspcmcia and pccardctl, as well as cating /sys (which is apparently
pretty much what udevinfo does as well)
udev can be a bit tricky. You might check to see if
Quoting [EMAIL PROTECTED]:
Quoting Tom Sylla [EMAIL PROTECTED]:
[EMAIL PROTECTED] wrote:
So, I should just need to clear any parity and serr errors after
pci_bus_enable_resources() function runs but before the
pci_dev_enable_resources() function runs. Like this:
Well, my suggestion was
On 9/16/07, Uwe Hermann [EMAIL PROTECTED] wrote:
On Wed, Aug 29, 2007 at 09:18:47PM -0700, ron minnich wrote:
We have to test this, so please, no acks without a test. I will try to
test tomorrow.
Any news on this?
I ran into bad troubles with my msm800 but it is fixed, as of last
week; will
On 16/09/07 16:53 +0200, Uwe Hermann wrote:
I'm not so sure. Maybe it actually _is_ a good idea to integrate (parts
of) buildrom in the v3 build process? It would sure make the
user experience better. The question is how much work this will be.
I guess we'd want to change quite a lot of
On 16/09/07 15:08 -0300, Alan Carvalho de Assis wrote:
2007/9/16, Uwe Hermann [EMAIL PROTECTED]:
I'm not so sure. Maybe it actually _is_ a good idea to integrate (parts
of) buildrom in the v3 build process? It would sure make the
user experience better. The question is how much work this
On Sun, Sep 16, 2007 at 08:47:27PM -0400, Ward Vandewege wrote:
Here's an lspci of the pci bridge (device 06.0), booted from the
proprietary bios:
..
and from linuxbios:
--- pcib.f 2007-09-17 18:21:34.0 +0200
+++ pcib.lb 2007-09-17 18:21:53.0 +0200
@@ -1,15 +1,15 @@
On Sun, Sep 16, 2007 at 10:23:08PM -0500, David H. Barr wrote:
I'll be very pleased to work with someone to set this up for
automatic testing, if that sort of thing interests anyone.
Certainly! It would be great to get more boards into testing.
I have two boards, BIOS-Saviors, and remote
Ward Vandewege wrote:
Hi there,
We've had a bit of a chat on the IRC channel today about the M57SLI and how
the pci bridge does not seem to be initialized properly under LinuxBIOS. The
pci-e bridge is initialized ok - pci-e vga cards work fine; pci vga cards
do not.
Here's an lspci of
On 9/16/07, Richard Wei [EMAIL PROTECTED] wrote:
Ha~ it works now after changed to 64bit kernel.
Thanks ^_^
But still wondering why it only support 64bit kernel.
What should we do to make the 32bit kernel support possible?
So could be 32bit kernel problem. you could dig out why the 32bit
Hi,
On Mon, Sep 17, 2007 at 10:43:35AM +0300, Markus Tornqvist wrote:
The problem: I'm not seeing the cflash /dev/hde. It's found a-ok by
lspcmcia and pccardctl, as well as cating /sys (which is apparently
pretty much what udevinfo does as well)
udev can be a bit tricky. You might check to
1. 64 bit kernel? I never tried 32 bit kernel...
2. nothing to with irq.
3. boot log wht pci_vga card?
YH
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Hi gentlemens,
Quoting yhlu [EMAIL PROTECTED]:
1. 64 bit kernel? I never tried 32 bit kernel...
I have done tests with both types (32b 64b)= same results!
2. nothing to with irq.
Ok
3. boot log wht pci_vga card?
The boot log that i have send (which encompasses both LinuxBIOS and Linux
On 9/17/07, Peter Stuge [EMAIL PROTECTED] wrote:
On Sun, Sep 16, 2007 at 10:23:08PM -0500, David H. Barr wrote:
I have two boards, BIOS-Saviors, and remote reboot capability.
Do you mind hacking a bit? The scripts are currently designed for a
network-based power switch, but it should be
Hi Yinghai,
On Mon, Sep 17, 2007 at 08:40:41PM +0200, [EMAIL PROTECTED] wrote:
1. 64 bit kernel? I never tried 32 bit kernel...
I have done tests with both types (32b 64b)= same results!
2. nothing to with irq.
Ok
3. boot log wht pci_vga card?
The boot log that i have send (which
On 9/17/07, Ward Vandewege [EMAIL PROTECTED] wrote:
I've attached that boot log to this message.
the one without any vga card installed?
Can you post one with pcie display card installed and the one with pci
display card installed?
YH
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#65: Unify SuperIO code?
+---
Reporter: stepan | Owner: somebody
Type: enhancement |Status: new
Priority: minor| Milestone: Cosmetic fixes
#86: filo sata boot delay patch
---+
Reporter: ward| Owner: somebody
Type: defect |Status: new
Priority: major | Milestone:
Component:
On Fri, Sep 14, 2007 at 01:31:48PM -0600, Marc Jones wrote:
I suspect that this is the SPD address is different.
How do I find out the correct one? i2cdetect/i2cdump?
I think that a scan with i2cdump would be your best bet.
It turns out the code was working already, it's just that some
On Sun, Sep 16, 2007 at 06:56:55PM -0700, Jonathan Sturges wrote:
Thanks Uwe,
That was it! I added 'option IRQ_SLOT_COUNT=3' to the Config.lb in the
target directory of my board, and that did the trick. I now get IRQs
assigned to all 3 devices I intended to. Very nice!
Nice, indeed! Does
On Sun, Sep 16, 2007 at 10:23:08PM -0500, David H. Barr wrote:
Other than that this is a very nice new target, a relatively cheap,
modern K8+MCP55 board, with _socketed_ PLCC chip!
I'll be very pleased to work with someone to set this up for automatic
testing, if that sort of thing
On Fri, Sep 14, 2007 at 08:31:29PM +0300, Jouni Mettälä wrote:
I tried to flash. MS-6337 with recently added MS-6178. It was needed to put
WP# and TBL# pins to high but since another chip is in use it is ok.
With filo as payload, post card gave 10 ... pause... 80, f8, fe ..short
pause and
On Mon, Sep 17, 2007 at 09:06:19AM -0400, [EMAIL PROTECTED] wrote:
Well I figured out what the problem is. I have a parity error in the
PD_STS?Primary Device Status Register 0x06 and can't clear the bit 15.
When I try it just goes back to 0x8080. I am supposed to be able to
clear this bit
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer uwe checked in revision 2780 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Add a README for superiotool (trivial).
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
On Sun, Sep 16, 2007 at 06:56:55PM -0700, Jonathan Sturges wrote:
Thanks Uwe,
That was it! I added 'option IRQ_SLOT_COUNT=3' to the Config.lb in the
target directory of my board, and that did the trick. I now get IRQs
assigned to all 3 devices I intended to. Very nice!
Nice, indeed! Does
On 9/16/07, Jonathan Sturges [EMAIL PROTECTED] wrote:
As a side note, I noticed that only 2 boards came with IRQ_SLOT_COUNT in
their Config.lb's. Was this option recently made mandatory? If so, we need
a sweep to update the LBv2 Config.lb files.
This option was always needed, due to bugs
[EMAIL PROTECTED] wrote:
Here you go Uwe,
i82830 northbridge code is done. Works great. Note: Checkout the
generic spd_get_dimm_size()function in raminit.c, there is a pretty
cool way to get each side of a dimm's size only using SPD 5 and 31
(original idea from Corey, Thanks). Works for dimms
On 9/17/07, Uwe Hermann [EMAIL PROTECTED] wrote:
If you get a chance to try this on your board(s), please post your boot
logs and check whether you see problems with PCI add-on cards (e.g.
PCI VGA cards).
Also, if you could try a PCI Express VGA (or other) card, that would be nice.
If I'm
*ping*
Anybody a idea how to get this bug done?
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