Hi.
I have the same problem with iei/juki-511 and iei/lx-800.
This patch allow to load from slave.
--
Nikolay
diff -Nru filo-0.5/drivers/ide.c filo-0.5-slave/drivers/ide.c
--- filo-0.5/drivers/ide.c 2006-09-06 13:43:26.0 +0600
+++ filo-0.5-slave/drivers/ide.c 2007-09-17
OK, I have a new booting problem. LB dies on the
i82801xx_enable_ioapic() function in 82801xx_lpc.c:
void i82801xx_enable_ioapic(struct device *dev)
{
uint32_t reg32;
volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec0;
volatile uint32_t *ioapic_data =
Quoting [EMAIL PROTECTED]:
OK, I have a new booting problem. LB dies on the
i82801xx_enable_ioapic() function in 82801xx_lpc.c:
void i82801xx_enable_ioapic(struct device *dev)
{
uint32_t reg32;
volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec0;
volatile
[EMAIL PROTECTED] wrote:
OK, I have a new booting problem. LB dies on the
i82801xx_enable_ioapic() function in 82801xx_lpc.c:
void i82801xx_enable_ioapic(struct device *dev)
{
uint32_t reg32;
volatile uint32_t *ioapic_index = (volatile uint32_t *)0xfec0;
volatile
On Thu, Sep 27, 2007 at 10:19:57AM -0700, ron minnich wrote:
OK, I like signed offset, but let's let stefan weigh in. It's critical
that we get this right.
I don't have any particular opinion here, but I'll NACK the patch in
this form. If everybody else agrees with the patch _and_ there are at
On Thu, Sep 27, 2007 at 06:54:28PM +0200, Carl-Daniel Hailfinger wrote:
Well, as I said, I tested superiotool on multiple machines. I should
be able to just crack the case on a machine and spot it on the
motherboard, I assume?
Yes, but we'll probably be able to tell it from the short
On 28.09.2007 15:33, Uwe Hermann wrote:
On Thu, Sep 27, 2007 at 10:19:57AM -0700, ron minnich wrote:
OK, I like signed offset, but let's let stefan weigh in. It's critical
that we get this right.
I don't have any particular opinion here, but I'll NACK the patch in
this form. If everybody
On Thu, Sep 27, 2007 at 08:31:16PM +0200, Stefan Reinauer wrote:
* Uwe Hermann [EMAIL PROTECTED] [070927 19:14]:
No duplicated code whatsoever. Sure, this may not be too elegant
(there's some room for improvements, though), but it's definately a
_lot_ better than duplicating all those
On 27.09.2007 16:30, Ward Vandewege wrote:
On Thu, Sep 27, 2007 at 11:31:14AM +0200, Carl-Daniel Hailfinger wrote:
No problem. Can you commit with your changes? Changelog follows:
Add preliminary SPI flash identification support for SPI chips attached
to ITE IT8716F Super I/O. Right now this
Quoting [EMAIL PROTECTED]:
Quoting [EMAIL PROTECTED]:
OK, I have a new booting problem. LB dies on the
i82801xx_enable_ioapic() function in 82801xx_lpc.c:
void i82801xx_enable_ioapic(struct device *dev)
{
uint32_t reg32;
volatile uint32_t *ioapic_index = (volatile uint32_t
On Thu, Sep 27, 2007 at 10:21:56PM +0200, Robert Millan wrote:
I strongly disagree with this approach. Duplicated code is bad, bad,
bad and should be avoided whereever possible.
If we look at it in perspective, I think the cons for each option can be
summarised as:
- duplicate:
Author: uwe
Date: 2007-09-28 17:39:10 +0200 (Fri, 28 Sep 2007)
New Revision: 2813
Added:
trunk/util/superiotool/ali.c
Modified:
trunk/util/superiotool/Makefile
trunk/util/superiotool/fintek.c
trunk/util/superiotool/superiotool.h
Log:
Add support for some more Fintek chips and an ALi
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer uwe checked in revision 2814 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Random minor fixes. Use svn revision as superiotool version number.
Make the -V output
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer uwe checked in revision 2812 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Fix up the SMSC detection code to probe _both_ old- and new-style
Super I/Os from SMSC.
On Thu, Sep 27, 2007 at 02:46:09PM -0700, ron minnich wrote:
On 9/27/07, Robert Millan [EMAIL PROTECTED] wrote:
- include: someone might break board A in a commit that was only tested
on board B.
I can only say it's been a huge problem in the past. I've had cases
where I tried to
On Thu, Sep 27, 2007 at 05:44:29PM +0200, Peter Stuge wrote:
On Thu, Sep 27, 2007 at 04:20:28PM +0200, Robert Millan wrote:
I just wrote a small utility to set the appropiate bytes in
linuxbios.rom.
Any comments?
I prefer the xxd trick. Note that I am exclusively working on systems
Hi,
On Thursday 27 September 2007 16:44, Marco Tralli wrote:
I have random hangs on kernel boot or after few minutes on a NatSemi Geode
GX1 based PC-104 (from Advantech) using kernel 2.6.23-rc6. The system
locks, no way to use SysRq key, no usefull logs.
No problems using kernel 2.6.21
On 28.09.2007 17:45, [EMAIL PROTECTED] wrote:
Author: uwe
Date: 2007-09-28 17:45:43 +0200 (Fri, 28 Sep 2007)
New Revision: 2814
Log:
Random minor fixes. Use svn revision as superiotool version number.
Make the -V output more informative.
Signed-off-by: Uwe Hermann [EMAIL PROTECTED]
On Fri, Sep 28, 2007 at 03:35:54PM +0200, Carl-Daniel Hailfinger wrote:
On 27.09.2007 16:30, Ward Vandewege wrote:
On Thu, Sep 27, 2007 at 11:31:14AM +0200, Carl-Daniel Hailfinger wrote:
No problem. Can you commit with your changes? Changelog follows:
Add preliminary SPI flash
Author: uwe
Date: 2007-09-28 17:02:17 +0200 (Fri, 28 Sep 2007)
New Revision: 2812
Modified:
trunk/util/superiotool/smsc.c
Log:
Fix up the SMSC detection code to probe _both_ old- and new-style
Super I/Os from SMSC. Otherwise not all of them are detected (and there
could theoretically be _two_
OK, these mobos are close enough to each other to share most code. Let
me throw out a challenge to this group. Make the bios image that runs
on each board *IDENTICAL*. You can figure out what each board is --
can you tell by which superio it is or something? -- and then case out
in runtime.
Why
Dear LinuxBIOS readers!
This is the automated build check service of LinuxBIOS.
The developer uwe checked in revision 2813 to
the LinuxBIOS source repository and caused the following
changes:
Change Log:
Add support for some more Fintek chips and an ALi chip.
Signed-off-by: Uwe Hermann [EMAIL
[EMAIL PROTECTED] wrote:
Quoting [EMAIL PROTECTED]:
Quoting [EMAIL PROTECTED]:
OK, I have a new booting problem. LB dies on the
i82801xx_enable_ioapic() function in 82801xx_lpc.c:
void i82801xx_enable_ioapic(struct device *dev)
{
uint32_t reg32;
volatile uint32_t
Author: uwe
Date: 2007-09-28 17:45:43 +0200 (Fri, 28 Sep 2007)
New Revision: 2814
Modified:
trunk/util/superiotool/Makefile
trunk/util/superiotool/ali.c
trunk/util/superiotool/fintek.c
trunk/util/superiotool/ite.c
trunk/util/superiotool/nsc.c
trunk/util/superiotool/smsc.c
On Fri, Sep 28, 2007 at 03:34:52PM +0200, Uwe Hermann wrote:
On Mon, Sep 24, 2007 at 05:37:30PM -0700, ron minnich wrote:
On 9/24/07, Uwe Hermann [EMAIL PROTECTED] wrote:
This may be a stupid question, but is it possible to put kexec in the
ROM, too? Yes, it consumes some space, but
On Thu, Sep 27, 2007 at 03:56:20PM +0200, Carl-Daniel Hailfinger wrote:
Please provide a diff between dmesg under LB and proprietary BIOS. I
suspect some keyboard init is done differently.
Here.
--
Robert Millan
GPLv2 I know my rights; I want my phone call!
DRM What use is a phone call, if
On 28/09/07 14:54 -0400, Ward Vandewege wrote:
On Fri, Sep 28, 2007 at 03:34:52PM +0200, Uwe Hermann wrote:
On Mon, Sep 24, 2007 at 05:37:30PM -0700, ron minnich wrote:
On 9/24/07, Uwe Hermann [EMAIL PROTECTED] wrote:
This may be a stupid question, but is it possible to put kexec in
On 9/28/07, Jordan Crouse [EMAIL PROTECTED] wrote:
I've said it before, and I'll say it again. We need a minimal version of
Kconfig for 32bit x86 a ukexec if you will (but please don't use that name).
It can be either tied into Busybox, or stand on its own - I don't really
think it matters.
On 28.09.2007 22:16, ron minnich wrote:
On 9/28/07, Jordan Crouse [EMAIL PROTECTED] wrote:
I've said it before, and I'll say it again. We need a minimal version of
Kconfig for 32bit x86 a ukexec if you will (but please don't use that name).
It can be either tied into Busybox, or stand on its
On 28.09.2007 21:14, Robert Millan wrote:
On Thu, Sep 27, 2007 at 03:56:20PM +0200, Carl-Daniel Hailfinger wrote:
Please provide a diff between dmesg under LB and proprietary BIOS. I
suspect some keyboard init is done differently.
Here.
There's quite some stuff broken. Comments below.
On 9/28/07, ron minnich [EMAIL PROTECTED] wrote:
OK, these mobos are close enough to each other to share most code. Let
me throw out a challenge to this group. Make the bios image that runs
on each board *IDENTICAL*. You can figure out what each board is --
can you tell by which superio it is
On 28/09/07 11:05 -0700, ron minnich wrote:
OK, these mobos are close enough to each other to share most code. Let
me throw out a challenge to this group. Make the bios image that runs
on each board *IDENTICAL*. You can figure out what each board is --
can you tell by which superio it is or
On 9/28/07, yhlu [EMAIL PROTECTED] wrote:
how to figure out who's who?
some pci device that is on one but not another
superio id
not sure what else.
ron
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linuxbios mailing list
linuxbios@linuxbios.org
http://www.linuxbios.org/mailman/listinfo/linuxbios
ron minnich wrote:
On 9/28/07, yhlu [EMAIL PROTECTED] wrote:
how to figure out who's who?
some pci device that is on one but not another
superio id
not sure what else.
ron
In the case that they're actually provided and updated correctly,
subsystem vendor/model ids.
-Corey
This is tested, it has one small different from the earlier patch.
I don't know where else to send the patch.
ron
Fix filo so that it can run with IDE channels that only have slaves.
Tested on the MSM800SEV, with master only, master and slave,
and slave only.
From a patch by Nikolay Petukhov
Have three motherboards running cn700, VT8237 chips set. All three
boards have W39V040BPZ bios chips. I can not program them with
flashrom. Flashrom see the chip as W39V040B. Flashrom start on the
flash and just sits there. When flashed with the -V option I can see
the memory address is not
On 9/28/07, Adam Talbot [EMAIL PROTECTED] wrote:
Have three motherboards running cn700, VT8237 chips set. All three
boards have W39V040BPZ bios chips. I can not program them with
flashrom. Flashrom see the chip as W39V040B. Flashrom start on the
flash and just sits there. When flashed
Adam Talbot wrote:
Have three motherboards running cn700, VT8237 chips set. All three
boards have W39V040BPZ bios chips. I can not program them with
flashrom. Flashrom see the chip as W39V040B. Flashrom start on the
flash and just sits there. When flashed with the -V option I can see
the
Yep, my jetway has that. It is off. But I have not tried flashrom on
that board. Can not seem to get the stock BIOS to boot from USB. The
other two boards are PCChips V21G V1.0C
-Adam
Corey Osgood wrote:
Adam Talbot wrote:
Have three motherboards running cn700, VT8237 chips set. All
Thanks Ron, here is what is hiding in MTRR, explanation?
v21g ~ # cat /proc/mtrr
reg00: base=0x ( 0MB), size= 512MB: write-back, count=1
reg01: base=0x1f00 ( 496MB), size= 16MB: uncachable, count=1
reg02: base=0xe800 (3712MB), size= 128MB: write-combining, count=2
reg03:
On Fri, Sep 28, 2007 at 10:41:00PM +0200, Carl-Daniel Hailfinger wrote:
/proc/interrups /proc/ioports /proc/iomem
would also be useful to compare.
Here.
--
Robert Millan
GPLv2 I know my rights; I want my phone call!
DRM What use is a phone call, if you are unable to speak?
(as seen on /.)
Adam Talbot wrote:
Yep, my jetway has that. It is off. But I have not tried flashrom on
that board. Can not seem to get the stock BIOS to boot from USB.
It's a pain in the rear. Boot the board with the USB flash drive plugged
in. Depending on if you have a hard drive installed or not, shut it
On 9/28/07, Corey Osgood [EMAIL PROTECTED] wrote:
subsystem vendor/model ids.
LinuxBIOS is supposed to set up those.
YH
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http://www.linuxbios.org/mailman/listinfo/linuxbios
yhlu wrote:
On 9/28/07, Corey Osgood [EMAIL PROTECTED] wrote:
subsystem vendor/model ids.
LinuxBIOS is supposed to set up those.
YH
Oops, yeah, my bad. Not sure what I was thinking
-Corey
--
linuxbios mailing list
linuxbios@linuxbios.org
On 9/28/07, Adam Talbot [EMAIL PROTECTED] wrote:
Thanks Ron, here is what is hiding in MTRR, explanation?
v21g ~ # cat /proc/mtrr
reg00: base=0x ( 0MB), size= 512MB: write-back, count=1
reg01: base=0x1f00 ( 496MB), size= 16MB: uncachable, count=1
reg02: base=0xe800
On 28.09.2007 16:55, Uwe Hermann wrote:
On Fri, Sep 28, 2007 at 03:35:54PM +0200, Carl-Daniel Hailfinger wrote:
On 27.09.2007 16:30, Ward Vandewege wrote:
On Thu, Sep 27, 2007 at 11:31:14AM +0200, Carl-Daniel Hailfinger wrote:
No problem. Can you commit with your changes? Changelog follows:
Thanks to Carl-Daniel's help in debugging my keyboard problems, it seems we
found what's wrong. During boot log:
PNP: 002e.8 missing set_resources
PNP: 002e.9 missing set_resources
PNP: 002e.a missing set_resources
ERROR: PNP: 002e.1 60 io size: 0x08 not assigned
ERROR: PNP:
-Ron
Just tried the Jetway board. Flashed just fine. Seems to be a problem
with the PCChips board. What should I start checking?
-Adam
ron minnich wrote:
On 9/28/07, Adam Talbot [EMAIL PROTECTED] wrote:
Thanks Ron, here is what is hiding in MTRR, explanation?
v21g ~ # cat /proc/mtrr
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
This patch fixes the resource end in amdk8/northbridge.c
Signed-off-by: Rudolf Marek [EMAIL PROTECTED]
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.6 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello,
Following patch adds MCFG table for ACPI, so linux can find MMCONFIG area for
PCI configuration access.
Please note that you need to hack Linux kernel and remove the check for e820 not
reserved complain.
Signed-off-by: Rudolf Marek [EMAIL
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello,
This patch changes the if else style of parameter matching to table and also
changes the rdpreamble parameter, which will cause that more then one DIMM will
work for 939 motherboard.
What about the 2T support?
Please take a look to a patch
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello all,
I'm attaching quite big patch which adds support for the K8T890/VT8237R chipset
and for my motherboard Asus A8V-E SE.
It works fine except for reboot, I'm using it daily ;) Now I need help with the
release.
I have done some modifications
Hello, all!
I would like to use the BIOS in my old lap-top, Toshiba Satellite 320CDS,
but I wasn't able to find if it is supported or not.
Do some know this or know how can I find out?
This site got some info related to this notebook specs:
http://www.ciao.co.uk/Toshiba_Satellite_320CDS__6517090
On 9/28/07, Adam Talbot [EMAIL PROTECTED] wrote:
-Ron
Just tried the Jetway board. Flashed just fine. Seems to be a problem
with the PCChips board. What should I start checking?
the partial flash is very confusing. That's usually a caching
interaction. But MTRRs are not set to cache that
Hi,
[you managed to trigger a bug in my Seamonkey mail client with your
mail. The mail contents started scrolling upward automatically and
reproducibly. Nice.]
On 29.09.2007 02:10, Rudolf Marek wrote:
Hello,
This patch changes the if else style of parameter matching to table and also
On 29.09.2007 02:02, Rudolf Marek wrote:
This patch fixes the resource end in amdk8/northbridge.c
Signed-off-by: Rudolf Marek [EMAIL PROTECTED]
If this fixes resources going backwards, it is
Acked-by: Carl-Daniel Hailfinger [EMAIL PROTECTED]
Can somebody please commit?
Rudolf
On 29.09.2007 02:05, Rudolf Marek wrote:
Hello,
Following patch adds MCFG table for ACPI, so linux can find MMCONFIG area for
PCI configuration access.
Please note that you need to hack Linux kernel and remove the check for e820
not
reserved complain.
Signed-off-by: Rudolf Marek
On 29.09.2007 03:17, Carl-Daniel Hailfinger wrote:
On 29.09.2007 02:05, Rudolf Marek wrote:
Hello,
Following patch adds MCFG table for ACPI, so linux can find MMCONFIG area for
PCI configuration access.
Please note that you need to hack Linux kernel and remove the check for e820
not
This patch aims to restructure SPI flash support in a more reasonable
way. It introduces a generic SPI host driver for the IT8716F Super I/O
which will enable easy SPI programming without having to care for the
peculiarities of the SPI host.
To activate probing for the IT8716F, you have to use
On 9/28/07, Rafael [EMAIL PROTECTED] wrote:
Hello, all!
I would like to use the BIOS in my old lap-top, Toshiba Satellite 320CDS,
but I wasn't able to find if it is supported or not.
Do some know this or know how can I find out?
When you say use the BIOS in my old lap-top, are you asking if
Hello!
Would one of you good people please provide something so that I may examine
this jetway board? A link for example would be very helpful.
--
Gregg C Levine [EMAIL PROTECTED]
The Force will be with you. Always. Obi-Wan Kenobi
-Original Message-
From: [EMAIL PROTECTED]
Gregg C Levine wrote:
Hello!
Would one of you good people please provide something so that I may examine
this jetway board? A link for example would be very helpful.
Jetway J7F2WE-series, support is in the works and nearly complete ;) I
only have a J7F2WE1G, but the CPU speed is
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