On Jan 7, 2008 2:45 PM, Marc Jones <[EMAIL PROTECTED]> wrote:
> As for 1MB and above, it sounds like GLIUInit() isn't running correctly.
> Can you dump RCONF and GLIU MSRs? Something like v2 print_conf() in the
> norwich\mainboard.c.
I'm bringing that code forward but some MSRs got renamed, so g
ron minnich wrote:
> v3 loads and runs on an alix1c.
>
> So far, the only payload that works is a RET. Even a simple OUTB
> followed by a RET fails.
>
> Any ideas on this? I'm flummoxed. Could it be the stack location?
> Stack is at 0x8fxxx.
>
> Also, I have to run at < 1 MB, the memory above
On 05.01.2008 02:36, ron minnich wrote:
> v3 loads and runs on an alix1c.
> [...]
> Also, I have to run at < 1 MB, the memory above 1 MB reads back as all
> .
>
arch/x86/geodelx/stage1.c has two very interesting comments:
/* Setup access to cache under 1MB. */
[...]
/* Setup acces
On 05.01.2008 02:36, ron minnich wrote:
> v3 loads and runs on an alix1c.
>
> So far, the only payload that works is a RET. Even a simple OUTB
> followed by a RET fails.
>
outb and ret in asm? If not, we may have problems with the state of the
registers the called program expects.
It would be i
v3 loads and runs on an alix1c.
So far, the only payload that works is a RET. Even a simple OUTB
followed by a RET fails.
Any ideas on this? I'm flummoxed. Could it be the stack location?
Stack is at 0x8fxxx.
Also, I have to run at < 1 MB, the memory above 1 MB reads back as all .
that'
On 13.11.2007 02:35, Carl-Daniel Hailfinger wrote:
> On 12.11.2007 18:07, Marc Jones wrote:
>
>> Carl-Daniel Hailfinger wrote:
>>
>>> while taking a look at stage0 and stage1 code in v3, I was surprised to
>>> see no coherent structure in the code for Geode LX boards.
>>> While some of this
On 12.11.2007 18:07, Marc Jones wrote:
> Carl-Daniel Hailfinger wrote:
>>
>> while taking a look at stage0 and stage1 code in v3, I was surprised to
>> see no coherent structure in the code for Geode LX boards.
>> While some of this may be due to dead code, I'd like to know:
>> * which board can se
Carl-Daniel Hailfinger wrote:
> Hi,
>
> while taking a look at stage0 and stage1 code in v3, I was surprised to
> see no coherent structure in the code for Geode LX boards.
> While some of this may be due to dead code, I'd like to know:
> * which board can serve as structural reference
> * which bo
Hi,
while taking a look at stage0 and stage1 code in v3, I was surprised to
see no coherent structure in the code for Geode LX boards.
While some of this may be due to dead code, I'd like to know:
* which board can serve as structural reference
* which board is working best.
Once I know that, I c
On 10/27/07, Corey Osgood <[EMAIL PROTECTED]> wrote:
> Hmm, I have no geode (except an NX kicking around somewhere), but I'm
> looking at the c7, cn700, and vt8237r. I've ported most of the
> northbridge and superio code, next comes the southbridge.
Let's start getting your patches in the tree in
ron minnich wrote:
> no hardware on v3. There is an almost-done geode port.
>
> We can use the help
>
> ron
>
Hmm, I have no geode (except an NX kicking around somewhere), but I'm
looking at the c7, cn700, and vt8237r. I've ported most of the
northbridge and superio code, next comes the southbr
no hardware on v3. There is an almost-done geode port.
We can use the help
ron
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Okay, just wondering, what's the current state of v3? Is any hardware
booting on it yet? Where does work need to be done? I thought there was
a wiki page on this, but I can't seem to find it now.
Thanks,
Corey
PS: Sorry if this hits the list more then once, working from a very bad
wireless connec
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