On Tue, Nov 25, 2008 at 7:45 AM, Lehmann, Hans (Ritter Elektronik)
wrote:
> Tim, Grant,
>
> just an info.
>
> Very often the Bestcomm-FEC crashed without any error logs if I initiate a
> transaction over FEC and save the file to disk (I rememeber I have read
> something like that). A restart of
On Tue, Nov 25, 2008 at 8:19 AM, Matt Sealey wrote:
>
>
> On Tue, Nov 25, 2008 at 8:45 AM, Lehmann, Hans (Ritter Elektronik)
> wrote:
>>
>> Tim, Grant,
>>
>> just an info.
>>
>> Very often the Bestcomm-FEC crashed without any error logs if I initiate a
>> transaction over FEC and save the file to
Sean MacLennan-2 wrote:
>
> On Fri, 19 Dec 2008 23:23:58 +0200
> "Felix Radensky" wrote:
>
>> Hi, Sean
>>
>> Do you have any ideas what can cause such delay ?
>
> Sorry, I haven't been following this thread :(
>
> We also use a 256M NAND, although a Spansion S29GL. While there is a
> small
On Fri, 19 Dec 2008 23:23:58 +0200
"Felix Radensky" wrote:
> Hi, Sean
>
> Do you have any ideas what can cause such delay ?
Sorry, I haven't been following this thread :(
We also use a 256M NAND, although a Spansion S29GL. While there is a
small delay in u-boot, there is no noticeable during t
On Fri, 2008-12-19 at 18:54 -0800, Kevin Diggs wrote:
> Hi,
>
> Is the thermal diode on a 970FX used on a G5? Can it be read by
> software?
The existing thermal control should do all you need already :-)
Cheers,
Ben.
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Hi,
Is the thermal diode on a 970FX used on a G5? Can it be read by
software?
kevin
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From: Grant Likely
This patch makes the default install script (arch/powerpc/boot/install.sh)
copy the bootable image files into the install directory. Before this
patch only the vmlinux image file was copied.
This patch makes the default 'make install' command useful for embedded
development w
From: Grant Likely
The MPC5200 internal interrupt controller setup function needs to set
the default interrupt controller when it is called. Without this
irq_create_of_mapping() cannot be called without first determining
the pointer to the irq controller (ie. call with controller = NULL).
Signe
The newest revision of uboot reworks the memory map for this
board to look more like the 85xx boards. Also, some regions
which were far larger than the actual hardware have been scaled
back to match the board, and the imaginary second flash bank has
been removed. Rapidio and PCI are mutually exclu
Stefan Roese wrote:
On Friday 19 December 2008, Felix Radensky wrote:
Thanks a lot to everyone who replied. I've managed to identify the cause
of the delay. The board is equipped with 256 MiB Samsung NAND flash.
Since NAND support is a must for this platform, I've intergated the ndfc
driver r
On Fri, 19 Dec 2008 08:44:57 +0300
Yuri Tikhonov wrote:
>
> The following patch fixes division by zero, which we have in
> shmem_truncate_range() and shmem_unuse_inode(), if use big
> PAGE_SIZE values (e.g. 256KB on ppc44x).
>
> With 256KB PAGE_SIZE the ENTRIES_PER_PAGEPAGE constant becomes
> t
This adds support for an EDAC memory controller adaptation driver for
the "ibm,sdram-4xx-ddr2" ECC controller realized in the AMCC PowerPC
405EX[r].
Signed-off-by: Grant Erickson
---
At present, this driver has been developed and tested against the
controller realization in the AMCC PPC405EX[r] o
The correct #address-cells was still used for the actual translation,
so the impact is only a possibility of choosing the wrong range entry
or failing to find any match. Most common cases were not affected.
Signed-off-by: Scott Wood
---
arch/powerpc/boot/devtree.c |2 +-
1 files changed, 1
Add const qualifier to device_node argument for
dcr_resource_{start,len} as of_get_property also const-qualifies this
argument.
Signed-off-by: Grant Erickson
---
arch/powerpc/include/asm/dcr.h |4 ++--
arch/powerpc/sysdev/dcr.c |5 +++--
2 files changed, 5 insertions(+), 4 deletions
On Dec 18, 2008, at 11:13 PM, Benjamin Herrenschmidt wrote:
This series of patches is aimed at supporting SMP on non-hash
based processors. It consists of a rework of the MMU context
management and TLB management, clearly splitting hash32, hash64
and nohash in both cases, adding SMP safe contex
- error cases for mapbase and irq were unbundled
- mapped irq now gets disposed on error
Signed-off-by: Wolfram Sang
---
Tested with 2.6.28-rc9 on a phyCORE-MPC5200B-IO.
Changes since V1:
after following a discussion on LKML, it seems better to:
- use -EINVAL again instead of -ENODEV
- use de
On Tue, Dec 16, 2008 at 9:41 PM, Wolfram Sang wrote:
>
>> It is pretty poor form to not even bother to Cc the only author of the
>> code you are modifying, and have no Signed-off-by or Acked-by to even
>> suggest that it was ever even looked at. This isn't something that ought
>> to have to be poi
On Fri, Dec 19, 2008 at 04:13:54PM +1100, Benjamin Herrenschmidt wrote:
>After discussing with chip designers, it appears that it's not
>necessary to set G everywhere on 440 cores. The various core
>errata related to prefetch should be sorted out by firmware by
>disabling icache prefetching in CCR0
On Fri, Dec 19, 2008 at 04:13:46PM +1100, Benjamin Herrenschmidt wrote:
>The handlers for Critical, Machine Check or Debug interrupts
>will save and restore MMUCR nowadays, thus we only need to
>disable normal interrupts when invalidating TLB entries.
>
>Signed-off-by: Benjamin Herrenschmidt
Acke
On Fri, Dec 19, 2008 at 04:13:22PM +1100, Benjamin Herrenschmidt wrote:
>This adds supports to the "extended" DCR addressing via
>the indirect mfdcrx/mtdcrx instructions supported by some
>4xx cores (440H6 and later)
>
>I enabled the feature for now only on AMCC 460 chips
>
>Signed-off-by: Benjamin
Stefan Roese wrote:
>
>
>> Is this an expected behavior - detection of 256 MiB NAND flash
>> takes around 20 seconds. The ndfc driver works fine after boot.
>
> No, 20 seconds is definitely too long. Something must be wrong with the
> ndfc
> driver or the NAND dts entries.
>
> Best regards,
Stefan Roese wrote:
>
>
>> Is this an expected behavior - detection of 256 MiB NAND flash
>> takes around 20 seconds. The ndfc driver works fine after boot.
>
> No, 20 seconds is definitely too long. Something must be wrong with the
> ndfc
> driver or the NAND dts entries.
>
> Best regards,
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