On Fri, 2009-04-17 at 11:26 +0300, Artem Bityutskiy wrote:
>
> I'm going to try to help you. I've just created a git tree where
> I'll push patches I consider OK and I approve. Here it is:
> git://git.infradead.org/users/dedekind/l2-mtd-2.6.git
>
> My hope is that you would look at that tree from
On Fri, 2009-06-05 at 14:05 +0200, Wolfram Sang wrote:
> Create an of-aware driver using the now exported generic functions from
> plat-ram.c. Also add the documentation for the binding. Partitions are
> not yet supported. Tested on a phyCORE-MPC5200B-IO.
Do we have an ack for the device-tree bind
On Fri, 2009-06-05 at 19:08 +1000, Stephen Rothwell wrote:
> Hi Michael,
>
> On Fri, 05 Jun 2009 17:38:40 +1000 Michael Ellerman
> wrote:
> >
> > On Fri, 2009-06-05 at 17:26 +1000, Stephen Rothwell wrote:
> > > Hi all,
> > >
> > > On Sun, 31 May 2009 15:09:50 +1000 Stephen Rothwell
> > > wrot
On Sat, Jun 06, 2009 at 09:14:08AM +0100, David Woodhouse wrote:
> On Fri, 2009-06-05 at 14:05 +0200, Wolfram Sang wrote:
> > Create an of-aware driver using the now exported generic functions from
> > plat-ram.c. Also add the documentation for the binding. Partitions are
> > not yet supported. Te
Hi All,
i have a freescale board, that contains MPC8555 processor & DSP-core
there is a GPIO connecting the DSP-core into an input pin of the OpenPIC of
the MPC8555 processor.
i test one interrupt from the DSP-core to the MPC8555 processor where i
configure this interrupt line to be edge-triggere
On Sat, Jun 6, 2009 at 9:17 AM, wael showair wrote:
>
> Hi All,
> i have a freescale board, that contains MPC8555 processor & DSP-core
> there is a GPIO connecting the DSP-core into an input pin of the OpenPIC of
> the MPC8555 processor.
>
> i test one interrupt from the DSP-core to the MPC8555 pro
On Saturday 06 June 2009, Greg KH wrote:
> Frank and Ian, any thoughts about the vmap call in the
> comedi_buf_alloc() call? Why is it using PAGE_KERNEL_NOCACHE, and what
> is the prealloc_buf buffer used for?
It is a circular buffer used to hold data streaming either to or from a
board (for exa
> "Joachim" == Joachim Foerster writes:
Hi,
Joachim> Any hints? Does anybody use SD card support with
Joachim> mmc_spi+xilinx_spi ?
I don't, but have you compared the spi signals on a scope in the 2
setups? Is timing significantly different?
--
Bye, Peter Korsgaard
_
On Fri, Jun 5, 2009 at 6:05 AM, Wolfram Sang wrote:
> diff --git a/Documentation/powerpc/dts-bindings/mtd-ram.txt
> b/Documentation/powerpc/dts-bindings/mtd-ram.txt
> new file mode 100644
> index 000..a2e9932
> --- /dev/null
> +++ b/Documentation/powerpc/dts-bindings/mtd-ram.txt
> @@ -0,0 +1,1
Am 06.06.09 18:05 schrieb(en) Grant Likely:
> + - bank-width : Width (in bytes) of the RAM bank.
Question: why is bank-width even relevant for a RAM device?
At least if the RAM is attached to the 5200's Local Plus Bus in 16-bit
mode, no byte write accesses are allowed (byte /reads/ work, tho
The PCIe MSI interrupts are missing from the device tree source, and
thus were not enabled. This patch adds them.
v2 of the patch fixes inconsistent white space, reported by David Gibson.
Tested to work on MPC8315E-RDB with custom FPGA PCIe device.
Signed-off-by: Leon Woestenberg
Tested-by: Leo
Hi Ben,
Here are some new commits to support the Xilinx ML507 board for 2.6.31
The following changes since commit baf75b0a42a1b3f6fca80f8949b6141eaff61b0d:
Stephen Rothwell (1):
powerpc/pci: Fix annotation of pcibios_claim_one_bus
are available in the git repository at:
git://git.se
The CHRP platform type only exists in a 32-bit build. Don't bother
checking machine_is(chrp) if we're in 64-bit mode.
Signed-off-by: David Woodhouse
diff --git a/arch/powerpc/platforms/powermac/setup.c
b/arch/powerpc/platforms/powermac/setup.c
index 45936c9..c22f7e8 100644
--- a/arch/powerpc/pl
From: Grant Likely
If anything goes wrong when copying images into the install path, then
the install script should exit with an error code so that 'make' knows
about it and tells the user.
Signed-off-by: Grant Likely
---
arch/powerpc/boot/install.sh |3 +++
1 files changed, 3 insertions(
Oops, forgot one. Here is a new request including the xilinxfb refactoring:
The following changes since commit baf75b0a42a1b3f6fca80f8949b6141eaff61b0d:
Stephen Rothwell (1):
powerpc/pci: Fix annotation of pcibios_claim_one_bus
are available in the git repository at:
git://git.secre
On Sat, Jun 6, 2009 at 7:34 AM, Jon Smirl wrote:
> On Sat, Jun 6, 2009 at 9:17 AM, wael showair wrote:
>>
>> Hi All,
>> i have a freescale board, that contains MPC8555 processor & DSP-core
>> there is a GPIO connecting the DSP-core into an input pin of the OpenPIC of
>> the MPC8555 processor.
>>
>>
Benjamin Herrenschmidt wrote:
No, Mel's patch is for a different problem and has been fixed upstream
already. This is more concerning... I'm not sure what's up but would
you be able to send a disassembly of the hpte_need_flush() function in
your kernel binary for me to see what access precisely c
On Sat, 2009-06-06 at 17:38 +0100, David Woodhouse wrote:
> The CHRP platform type only exists in a 32-bit build. Don't bother
> checking machine_is(chrp) if we're in 64-bit mode.
>
> Signed-off-by: David Woodhouse
Isn't the test bogus anyway ? It should be if (!machine_is(powermac))
but is usel
Currently the kernel expects the additional four IBAT and DBAT registers
to be available, but doesn't enable these registers on 745x CPUs, which
have them disabled after reset. Thus set the HIGH_BAT_EN bit in HID0
register, if the corresponding MMU feature is defined.
Signed-off-by: Gerhard Pirche
Am Fri, 5 Jun 2009 10:41:56 -0700 (PDT)
schrieb wael showair :
> My aim is : Each time the DSP-core interrupts the MPC8555 processor, a
> process in the user space will be informed by the arrival of this each
> interrupt.
You should have a look at drivers/uio...
> So i decided to use sw signals,
Dear David Jander,
In message <200903161652.09747.david.jan...@protonic.nl> you wrote:
> Complete workaround for DTLB errata in e300c2/c3/c4 processors.
>
> Due to the bug, the hardware-implemented LRU algorythm always goes to way
> 1 of the TLB. This fix implements the proposed software workarou
Dear John,
In message <4b73d43f0905071909v6e6e8b2el9eb6d4a1b9038...@mail.gmail.com> you
wrote:
>
> I think the fec's parent clock is the ipb clock not the ppc core clock.
> Could that be the problem?
I don't think so.
When debugging, I printed the actual clock frequencies, and they
looked as e
On Sun, 2009-06-07 at 00:07 +0200, Wolfgang Denk wrote:
> Dear David Jander,
>
> In message <200903161652.09747.david.jan...@protonic.nl> you wrote:
> > Complete workaround for DTLB errata in e300c2/c3/c4 processors.
> >
> > Due to the bug, the hardware-implemented LRU algorythm always goes to wa
On Sat, 2009-06-06 at 06:17 -0700, wael showair wrote:
> Hi All,
> i have a freescale board, that contains MPC8555 processor & DSP-core
> there is a GPIO connecting the DSP-core into an input pin of the OpenPIC of
> the MPC8555 processor.
>
> i test one interrupt from the DSP-core to the MPC8555 p
Dear John,
in message <4b73d43f0906061527p7ca1b301ybcfc576870a16...@mail.gmail.com> you
wrote:
>
> I noticed the latest BSP from Freescale has this patch:
>
> From: Chen Hongjun
> Date: Thu, 16 Apr 2009 20:22:52 +0800
> Subject: [PATCH] Fixed FEC bug for bluestone board.
>
> Signed-off-by: Che
Benjamin Herrenschmidt wrote:
>
> On Sat, 2009-06-06 at 06:17 -0700, wael showair wrote:
>> Hi All,
>> i have a freescale board, that contains MPC8555 processor & DSP-core
>> there is a GPIO connecting the DSP-core into an input pin of the OpenPIC
>> of
>> the MPC8555 processor.
>>
>> i test o
> > You cannot really rely on getting the exact same number of edge
> > interrupts that were emitted. At least not unless you have a hard RT
> > system and can guarantee that you'll always dequeue them fast enough.
>
> Yes, my system is a hard RT & i want to receive all the interrupts that
> have
Am Fri, 5 Jun 2009 10:41:56 -0700 (PDT)
schrieb wael showair :
> My aim is : Each time the DSP-core interrupts the MPC8555 processor, a
> process in the user space will be informed by the arrival of this each
> interrupt.
You should have a look at drivers/uio...
> So i decided to use sw signals,
I noticed the latest BSP from Freescale has this patch:
From: Chen Hongjun
Date: Thu, 16 Apr 2009 20:22:52 +0800
Subject: [PATCH] Fixed FEC bug for bluestone board.
Signed-off-by: Chen Hongjun
---
drivers/net/fs_enet/mii-fec.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff -
>
>
>
> The big question seems to be what the RefMan means when talking about
> the "system clock frequency". Obiously it is NOT the CPU clock as
> code variants above assume. The examples in "Table 17-24. Programming
> Examples for MII_SPEED Register" list "system clock frequencies" of
> 25,
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