On Fri, 2011-03-25 at 09:28 -0400, Eric B Munson wrote:
It is possible on POWER7 for some perf events to have values decrease. This
causes a problem with the way the kernel counters are updated. Deltas are
computed and then stored in a 64 bit value while the registers are 32 bits
wide so if
On Tue, 2011-03-29 at 16:37 +1100, Michael Ellerman wrote:
Takes a cpu parameter ..
+void generic_set_cpu_dead(unsigned int cpu)
+{
+ __get_cpu_var(cpu_state) = CPU_DEAD;
+}
But doesn't use it.
Yeah that's a bug. Fortunately it's always called on the current CPU :-)
I'll fix it
On 28.03.2011, at 21:25, Scott Wood wrote:
From: yu liu yu@freescale.com
We need to save/restore SPE environment on e500 core.
Wrap __kvmppc_vcpu_run() so that we can put the SPE code in
e500.c.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Scott Wood
On 28.03.2011, at 21:25, Scott Wood wrote:
From: yu liu yu@freescale.com
In order to use lazy SPE register save/restore, we need to
know when the guest is using MSR[SPE]. In order to do that, we
need to control the actual MSR[SPE] separately from the guest's
notion of MSR[SPE].
On 28.03.2011, at 21:25, Scott Wood wrote:
From: yu liu yu@freescale.com
This patch provide a lazy way to do SPE switch.
The SPE save/restore will be done only if it's needed.
Linux already switches SPEFSCR on context switch (non-lazily), so the
only remaining bit is to save it
On 29.03.2011, at 11:36, Liu Yu-B13201 wrote:
-Original Message-
From:
linuxppc-dev-bounces+b13201=freescale@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+b13201=freescale.com@lists.ozlabs
.org] On Behalf Of Alexander Graf
Sent: Tuesday, March 29, 2011 5:32 PM
To: Wood
-Original Message-
From:
linuxppc-dev-bounces+b13201=freescale@lists.ozlabs.org
[mailto:linuxppc-dev-bounces+b13201=freescale.com@lists.ozlabs
.org] On Behalf Of Alexander Graf
Sent: Tuesday, March 29, 2011 5:32 PM
To: Wood Scott-B07421
Cc: linuxppc-dev@lists.ozlabs.org
+static irqreturn_t dwc_otg_common_irq(int _irq, void *dev)
+{
+ struct dwc_otg_device *dwc_dev = dev;
+ int retval;
Tabify the declarations;
+
+ retval = dwc_otg_handle_common_intr(dwc_dev-core_if);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * This function is the
-Original Message-
From: linux-usb-ow...@vger.kernel.org
[mailto:linux-usb-ow...@vger.kernel.org] On Behalf Of
tma...@apm.com
Sent: Monday, March 28, 2011 11:58 PM
To: linux-...@vger.kernel.org; linuxppc-dev@lists.ozlabs.org
Cc: g...@kroah.com; tma...@apm.com
Subject: [PATCH v10
Hello.
On 28-03-2011 22:28, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
Enable gadget support
Signed-off-by: Tirumala R Marri tma...@apm.com
Signed-off-by: Fushen Chen fc...@apm.com
Signed-off-by: Mark Miesfeld mmiesf...@apm.com
[...]
diff --git
Hello.
On 28-03-2011 22:28, tma...@apm.com wrote:
From: Tirumala Marri tma...@apm.com
Add Synopsys DesignWare HS USB OTG driver kernel configuration.
Synopsys OTG driver may operate in host only, device only, or OTG mode.
The driver also allows user configure the core to use its internal
On Tue, 29 Mar 2011, Benjamin Herrenschmidt wrote:
On Fri, 2011-03-25 at 09:28 -0400, Eric B Munson wrote:
It is possible on POWER7 for some perf events to have values decrease. This
causes a problem with the way the kernel counters are updated. Deltas are
computed and then stored in a
Because of speculative event roll back, it is possible for some event coutners
to decrease between reads on POWER7. This causes a problem with the way that
counters are updated. Delta calues are calculated in a 64 bit value and the
top 32 bits are masked. If the register value has decreased,
On 03/25/2011 10:28 AM, Andre Schwarz wrote:
Grant, Anton,
got it.
providing modalis = spidev within spi_board_info works like a charme ...
Cheers,
André
we're about to get new MPC8377 based hardware with various
peripherals.
There are two I2C-to-SPI bridge devices (NXP SC18IS602) and I'm
On Tue, 29 Mar 2011 11:47:51 +0200
Alexander Graf ag...@suse.de wrote:
On 28.03.2011, at 21:25, Scott Wood wrote:
@@ -344,10 +345,19 @@ int kvmppc_handle_exit(struct kvm_run *run, struct
kvm_vcpu *vcpu,
r = RESUME_GUEST;
break;
- case
On Tue, 29 Mar 2011 11:37:44 +0200
Alexander Graf ag...@suse.de wrote:
On 28.03.2011, at 21:25, Scott Wood wrote:
From: yu liu yu@freescale.com
In order to use lazy SPE register save/restore, we need to
know when the guest is using MSR[SPE]. In order to do that, we
need to
On Tue, Mar 29, 2011 at 10:58:54AM +1100, Benjamin Herrenschmidt wrote:
On Mon, 2011-03-28 at 15:34 -0700, Sarah Sharp wrote:
What I'd like to do is take out the read of the status register out of
the interrupt handler (which is killing performance), and make it only
check the status
On Sunday, March 27, 2011 09:52:57 pm Matt Evans wrote:
On weakly-ordered systems, the reading of an event's content must occur
after reading the event's validity.
Signed-off-by: Matt Evans m...@ozlabs.org
---
Segher, thanks for the comment; explanation added.
Missed one instance when moving that to the core code.
Signed-off-by: Thomas Gleixner t...@linutronix.de
Cc: linuxppc-dev@lists.ozlabs.org
Cc: mich...@ellerman.id.au
Cc: mi...@elte.hu
---
arch/powerpc/platforms/cell/interrupt.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index:
On Sunday, March 27, 2011 09:53:00 pm Matt Evans wrote:
@@ -2282,7 +2284,7 @@ hw_died:
/* FIXME this should be a delayed service routine
* that clears the EHB.
*/
- xhci_handle_event(xhci);
+ while (xhci_handle_event(xhci)) {}
I must admit I dislike the style
On Tue, 2011-03-29 at 10:25 -0400, Eric B Munson wrote:
Here I made the assumption that the hardware would never remove more events in
a speculative roll back than it had added. This is not a situation I
encoutered in my limited testing, so I didn't think underflow was possible. I
will send
\
diff --git a/arch/powerpc/kernel/perf_event.c
b/arch/powerpc/kernel/perf_event.c
index 97e0ae4..0a5178f 100644
--- a/arch/powerpc/kernel/perf_event.c
+++ b/arch/powerpc/kernel/perf_event.c
@@ -416,6 +416,15 @@ static void power_pmu_read(struct perf_event *event)
prev =
On Tue, 2011-03-29 at 11:56 -0700, Dmitry Torokhov wrote:
+ /*
+ * Barrier between reading the TRB_CYCLE (valid) flag above
and any
+ * speculative reads of the event's flags/data below.
+ */
+ rmb();
/* FIXME: Handle more event types. */
switch
Hi all,
After merging the Linus' tree, today's linux-next build (powerpc
ppc64_defconfig) failed like this:
kernel/irq/chip.c: In function 'handle_edge_eoi_irq':
kernel/irq/chip.c:517: warning: label 'out_unlock' defined but not used
kernel/irq/chip.c:503: error: label 'out_eoi' used but not
Hi all,
After merging the Linus' tree, today's linux-next build (powerpc
ppc64_defconfig) failed like this:
arch/powerpc/platforms/cell/interrupt.c: In function 'iic_host_map':
arch/powerpc/platforms/cell/interrupt.c:247: error: 'handle_iic_irq' undeclared
(first use in this function)
Caused
On Wed, 2011-03-30 at 11:00 +1100, Stephen Rothwell wrote:
Hi all,
After merging the Linus' tree, today's linux-next build (powerpc
ppc64_defconfig) failed like this:
arch/powerpc/platforms/cell/interrupt.c: In function 'iic_host_map':
arch/powerpc/platforms/cell/interrupt.c:247: error:
On Wed, 2011-03-30 at 11:00 +1100, Stephen Rothwell wrote:
Hi all,
After merging the Linus' tree, today's linux-next build (powerpc
ppc64_defconfig) failed like this:
kernel/irq/chip.c: In function 'handle_edge_eoi_irq':
kernel/irq/chip.c:517: warning: label 'out_unlock' defined but not
Hi Linus !
Here are a few post -rc1 fixes for powerpc.
Mostly some more fallout from the irq core rework, new syscalls wireup,
defconfig fixes and minor bits. The only feature-esque thing in there
would be me adding dma_mmap_coherent(), it fixes various audio devices
on our older non
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