On Fri, 2013-07-26 at 08:09 +0530, Preeti U Murthy wrote:
> *The lapic of a broadcast CPU is active always*. Say CPUX, wants the
> broadcast CPU to wake it up at timeX. Since we cannot program the lapic
> of a remote CPU, CPUX will need to send an IPI to the broadcast CPU,
> asking it to program i
On 07/23/2013 11:01 AM, Deepthi Dharwar wrote:
> This patch enables idle powernv cpu to hook on to the cpuidle
> framework, if available, else call on to default idle platform
> code.
Why do you need to do that ?
> Signed-off-by: Deepthi Dharwar
> ---
> arch/powerpc/platforms/powernv/setup.c |
On 07/23/2013 11:01 AM, Deepthi Dharwar wrote:
> This patch implements a back-end cpuidle driver for
> powernv calling power7_nap and snooze idle states.
> This can be extended by adding more idle states
> in the future to the existing framework.
>
> Signed-off-by: Deepthi Dharwar
> ---
> arch/p
On Fri, Jul 26, 2013 at 04:31:34PM -0500, Ryan Arnold wrote:
> Adhemerval and I were just looking at the signal stack frames and I'd
> noticed the increase in size due to the addition of the HTM bits so this is
> great timing.
>
> I tried a sigstack.h patch that increased the values as you indicat
On 07/04/2013 07:54:12 AM, Kevin Hao wrote:
For a relocatable kernel since it can be loaded at any place, there
is no any relation between the kernel start addr and the
memstart_addr.
So we can't calculate the memstart_addr from kernel start addr. And
also we can't wait to do the relocation af
On 07/04/2013 07:54:13 AM, Kevin Hao wrote:
@@ -1222,6 +1266,9 @@ _GLOBAL(switch_to_as1)
/*
* Restore to the address space 0 and also invalidate the tlb entry
created
* by switch_to_as1.
+ * r3 - the tlb entry which should be invalidated
+ * r4 - __pa(PAGE_OFFSET in AS0) - pa(PAGE_OFFSET
On 07/04/2013 07:54:10 AM, Kevin Hao wrote:
We use the tlb1 entries to map low mem to the kernel space. In the
current code, it assumes that the first tlb entry would cover the
kernel image. But this is not true for some special cases, such as
when we run a relocatable kernel above the 256M or se
On 07/04/2013 07:54:09 AM, Kevin Hao wrote:
This is based on the codes in the head_44x.S. Since we always align to
256M before mapping the PAGE_OFFSET for a relocatable kernel, we also
change the init tlb map to 256M size.
Signed-off-by: Kevin Hao
---
v2: Move the code to set kernstart_addr and
On 07/04/2013 07:54:07 AM, Kevin Hao wrote:
diff --git a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
index a92c79b..2201f84 100644
--- a/arch/powerpc/kernel/fsl_booke_entry_mapping.S
+++ b/arch/powerpc/kernel/fsl_booke_entry_mapping.S
@@ -88,9 +
Alan Modra wrote on 07/26/2013 12:05:28 AM:
> Alan Modra
> 07/26/2013 12:05 AM
>
> To
>
> Anton Blanchard ,
>
> cc
>
> Michael Neuling , Ryan Arnold/Rochester/
> IBM@IBMUS, linuxppc-dev@lists.ozlabs.org
>
> Subject
>
> Re: SIGSTKSZ/MINSIGSTKSZ too small on 64bit
>
> On Fri, Jul 26, 2013 at 12:23
On 07/25/2013 07:54:53 AM, Kevin Hao wrote:
The reason is that the ppc kernel assume that the BARs starting
at 0 is unset and will reassign it later. There is a bug in the
previous
kernel, so the kernel maybe not work well for qemu in this case. But I
think this has been fixed by the commit c5
On 07/25/2013 03:50:42 AM, Gleb Natapov wrote:
Why ppc uses page_is_ram() for mmap? How should I know? But looking at
the function it does it only as a fallback if
ppc_md.phys_mem_access_prot() is not provided. Making access to MMIO
noncached as a safe fallback makes sense.
There's only one cur
On Fri, 2013-07-26 at 15:03 +, Bhushan Bharat-R65777 wrote:
> Will not searching the Linux PTE is a overkill?
That's the best approach. Also we are searching it already to resolve
the page fault. That does mean we search twice but on the other hand
that also means it's hot in the cache.
Cheer
On 07/26/2013 05:27:15 AM, hongbo.zh...@freescale.com wrote:
From: Hongbo Zhang
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this
patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
---
.../devicetree/bindings/powerpc/fsl/dma.txt| 66
++
On 07/25/2013 09:41:19 PM, Po Liu wrote:
+ partition@190 {
+ /* 7MB for User Area */
+ reg = <0x0190 0x0070>;
+ label = "NAND User area";
+ };
+
+ partition@200 {
+
On 07/25/2013 09:41:17 PM, Po Liu wrote:
+=
+Job Ring (JR) Node
+
+Child of the crypto node defines data processing interface to
SEC 6
+across the peripheral bus for purposes of processing
+cryptographic descriptor
On Thu, Jul 25, 2013 at 08:38:11AM +0800, Haijun Zhang wrote:
> Add voltage-range support in esdhc of T4, So we can choose
> to read voltages from dts file as one optional.
> If we can get a valid voltage-range from device node, we use
> this voltage as the final voltage support. Else we still read
On Mon, Jul 22, 2013 at 09:41:34PM -0500, Scott Wood wrote:
[...]
> >> > +static void esdhc_get_voltage(struct sdhci_host *host,
> >> > +struct platform_device *pdev)
> >> > +{
> >> > +}
> >>
> >> Don't duplicate this code. Move it somewhere common and share it.
> >[Ha
On Jul 25, 2013, at 5:02 PM, Andy Fleming wrote:
> T4, Cell, powernv, and pseries had the same implementation, so switch
> them to use a generic version. A2 apparently had a version, but
> removed it at some point, so we remove the declaration, too.
>
> Signed-off-by: Andy Fleming
>
> Conflict
On Jul 25, 2013, at 6:54 AM, Catalin Udma wrote:
> If CONFIG_E500 is enabled, the compilation flags are updated
> specifying the target core -mcpu=e5500/e500mc/8540
> Also remove -Wa,-me500, being incompatible with -mcpu=e5500/e6500
> The assembler option is redundant if the -mcpu= flag is set.
>
> -Original Message-
> From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
> Behalf Of Alexander Graf
> Sent: Friday, July 26, 2013 2:20 PM
> To: Benjamin Herrenschmidt
> Cc: Bhushan Bharat-R65777; kvm-...@vger.kernel.org; k...@vger.kernel.org;
> linuxppc-dev@lis
Hi Li,
On 07/26/2013 03:35 PM, Li Yang-R58472 wrote:
>
>
>> -Original Message-
>> From: linux-pm-ow...@vger.kernel.org [mailto:linux-pm-
>> ow...@vger.kernel.org] On Behalf Of Preeti U Murthy
>> Sent: Thursday, July 25, 2013 5:03 PM
>> To: b...@kernel.crashing.org; paul.gortma...@windriv
On Fri, Jul 26, 2013 at 11:19:13AM +1000, Anton Blanchard wrote:
>
> Hi Neil,
>
> > Sorry I'm a bit late to the thread, I've ben swamped. Has someone
> > tested this with kexec/kdump? Thats why the origional patch was
> > created, because when kexec loads the kernel at a different physical
> >
On Thu, Jul 25, 2013 at 10:57 AM, Bjorn Helgaas wrote:
> Convert pciehp to be builtin only, with no module option.
>
> Signed-off-by: Bjorn Helgaas
> Acked-by: Rafael J. Wysocki
> ---
> drivers/pci/pcie/Kconfig |5 +
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/driv
On Thu, Jul 25, 2013 at 10:57 AM, Bjorn Helgaas wrote:
> Convert CONFIG_HOTPLUG_PCI from tristate to bool. This only affects
> the hotplug core; several of the hotplug drivers can still be modules.
>
> Signed-off-by: Bjorn Helgaas
> ---
> arch/ia64/configs/generic_defconfig|2 +-
> arch
Hi Jean,
> -Original Message-
> From: Jean Delvare [mailto:jdelv...@suse.de]
> Sent: Friday, July 26, 2013 7:01 AM
... skip
> @@ -2246,11 +2246,11 @@ source "drivers/pcmcia/Kconfig"
> > source "drivers/pci/hotplug/Kconfig"
> >
> > config RAPIDIO
> > - bool "RapidIO support"
> >
On 07/26/2013 07:45 PM, Chen Gang wrote:
> c0080d30: 00 00 04 ac .long 0x4ac
> c0080d34: 60 00 00 00 nop
> c0080d38: 60 00 00 00 nop
> c0080d3c: 60 00 00 00 nop
> 816 case 'm':
> 817 cmd = inch
Hi Alexandre,
Le Friday 28 June 2013 à 15:18 -0400, Alexandre Bounine a écrit :
> Add a configuration option to build RapidIO subsystem core code as a loadable
> kernel module. Currently this option is available only for x86-based
> platforms,
> with the additional patch for PowerPC planned to be
From: Hongbo Zhang
This patch adds support to 8-channel DMA engine, thus the driver works for both
the new 8-channel and the legacy 4-channel DMA engines.
Signed-off-by: Hongbo Zhang
---
drivers/dma/Kconfig |9 +
drivers/dma/fsldma.c |9 ++---
drivers/dma/fsldma.h |2 +
From: Hongbo Zhang
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch adds
the device tree nodes for them.
Signed-off-by: Hongbo Zhang
---
.../devicetree/bindings/powerpc/fsl/dma.txt| 66
arch/powerpc/boot/dts/fsl/b4si-post.dtsi |
From: Hongbo Zhang
This patch updates the discription of each type of DMA controller and its
channels, it is preparation for adding another new DMA controller binding, it
also fixes some defects of indent for text alignment at the same time.
Signed-off-by: Hongbo Zhang
---
.../devicetree/bindi
From: Hongbo Zhang
Hi Vinod, Dan, Scott and Leo, please have a look at these V6 patches.
Freescale QorIQ T4 and B4 introduce new 8-channel DMA engines, this patch set
adds support this DMA engine.
V5->V6 changes:
- minor updates of descriptions in binding document and Kconfig
- remove [4/4], th
> -Original Message-
> From: linux-pm-ow...@vger.kernel.org [mailto:linux-pm-
> ow...@vger.kernel.org] On Behalf Of Preeti U Murthy
> Sent: Thursday, July 25, 2013 5:03 PM
> To: b...@kernel.crashing.org; paul.gortma...@windriver.com;
> pau...@samba.org; sha...@linux.vnet.ibm.com; ga...@ke
> -Original Message-
> From: kvm-ppc-ow...@vger.kernel.org [mailto:kvm-ppc-ow...@vger.kernel.org] On
> Behalf Of Alexander Graf
> Sent: Friday, July 26, 2013 2:20 PM
> To: Benjamin Herrenschmidt
> Cc: Bhushan Bharat-R65777; kvm-...@vger.kernel.org; k...@vger.kernel.org;
> linuxppc-dev@lis
> -Original Message-
> From: Benjamin Herrenschmidt [mailto:b...@kernel.crashing.org]
> Sent: Friday, July 26, 2013 1:57 PM
> To: Bhushan Bharat-R65777
> Cc: kvm-...@vger.kernel.org; k...@vger.kernel.org;
> linuxppc-dev@lists.ozlabs.org;
> ag...@suse.de; Wood Scott-B07421; Bhushan Bharat
On 26.07.2013, at 10:26, Benjamin Herrenschmidt wrote:
> On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
>> If the page is RAM then map this as cacheable and coherent (set "M" bit)
>> otherwise this page is treated as I/O and map this as cache inhibited
>> and guarded (set "I + G")
>>
On Fri, 2013-07-26 at 11:16 +0530, Bharat Bhushan wrote:
> If the page is RAM then map this as cacheable and coherent (set "M" bit)
> otherwise this page is treated as I/O and map this as cache inhibited
> and guarded (set "I + G")
>
> This helps setting proper MMU mapping for direct assigned dev
37 matches
Mail list logo
