On Thu, 2015-04-23 at 16:13 +0200, Jacek Anaszewski wrote:
> How the firmware is related to kernel? These bindings are for kernel,
> not for the firmware.
There should be no relation. DT bindings should be kernel agnostic and
represent the HW layout, not be designed based on what a given kernel
d
On Fri, 2015-04-24 at 12:15 +0200, Jacek Anaszewski wrote:
> No matter what format of device tree OPAL produces, I assume that
> it must compile it from some sources.
Nope. Well... .C code maybe qualifies as "sources" :-)
> dtb file is a compiled form of human readable dts file containing
> Flatt
On Sat, 2015-04-25 at 14:43 -0400, David Miller wrote:
> From: Michael Ellerman
> Date: Fri, 24 Apr 2015 15:52:32 +1000
>
> > The recent commit to only register the EHEA memory hotplug hooks on
> > adapter probe has a few problems.
> >
> > Firstly the reference counting is wrong for multiple ada
Four patches to cleanup the EEH, in type, comment and logic
---
v2:
* rebased on the latest kernel
Wei Yang (4):
powerpc/eeh: fix start/end/flags type in struct pci_io_addr_range{}
powerpc/eeh: fix comment for wait_state()
powerpc/eeh: fix powernv_eeh_wait_state delay logic
powerpc/eeh
struct pci_io_addr_range{} stores the information of pci resources. It
would be better to keep these related fields have the same type as in
struct resource{}.
This patch fixes the start/end/flags type in struct pci_io_addr_range{} to
have the same type as in struct resource{}.
Signed-off-by: Wei
To retrieve the PCI slot state, EEH driver would set a timeout for that.
While current comment is not aligned to what the code does.
This patch fixes those comments according to the code.
Signed-off-by: Wei Yang
Acked-by: Gavin Shan
---
arch/powerpc/kernel/eeh_driver.c |2 +-
a
As the comment indicates, powernv_eeh_get_state() will inform EEH core to
delay 1 second. This means the delay doesn't happen when
powernv_eeh_get_state() returns.
This patch moves the delay subtraction just before msleep(), which is the
same logic in pseries_eeh_wait_state().
Signed-off-by: Wei
Currently, the macro IS_BRIDGE is not used any where.
This patch just removes it.
Signed-off-by: Wei Yang
Acked-by: Gavin Shan
---
arch/powerpc/kernel/eeh.c |2 --
1 file changed, 2 deletions(-)
diff --git a/arch/powerpc/kernel/eeh.c b/arch/powerpc/kernel/eeh.c
index a4c62eb..4501bbb 10064
Load the PowerNV platform pci controller ops into pci controllers
after all the operations are loaded into the platform ops struct, not
before.
Fixes: c88c2a188905cb3077c3c38dc498e7e9f8eebeee
Reported-by: Gavin Shan
Signed-off-by: Daniel Axtens
---
arch/powerpc/platforms/powernv/pci-ioda.c | 2
On Mon, Apr 27, 2015 at 11:54:26AM +1000, Daniel Axtens wrote:
>Load the PowerNV platform pci controller ops into pci controllers
>after all the operations are loaded into the platform ops struct, not
>before.
>
>Fixes: c88c2a188905cb3077c3c38dc498e7e9f8eebeee
I think it would fix commit 65ebf4b63
Load the PowerNV platform pci controller ops into pci controllers
after all the operations are loaded into the platform ops struct, not
before.
Fixes: 65ebf4b63 ("powerpc/powernv: Move controller ops from ppc_md to
controller_ops")
Reported-by: Gavin Shan
Reviewed-by: Gavin Shan
Signed-off-by:
> >Fixes: c88c2a188905cb3077c3c38dc498e7e9f8eebeee
>
> I think it would fix commit 65ebf4b63 ("powerpc/powernv: Move controller ops
> from ppc_md to controller_ops")
> If that's the case, the above line could be replaced with:
>
> Fixes: 65ebf4b63 ("powerpc/powernv: Move controller ops from ppc_
On Fri, 2015-04-10 at 18:24 +1000, Alistair Popple wrote:
> Convert the opal ipmi driver to use the new irq interface for events.
> drivers/char/ipmi/ipmi_powernv.c | 39 ++-
This needs to be CC'ed to the IPMI folks, and preferably get their ACK so we
can take
On 22 April 2015 at 22:34, Shilpasri G Bhat
wrote:
> diff --git a/drivers/cpufreq/powernv-cpufreq.c
> b/drivers/cpufreq/powernv-cpufreq.c
> +static char throttle_reason[6][50] = { "No throttling",
Don't need to mention 6 here.
And the max length you need right now is 27, so maybe s/50/30 ?
Al
Hi Thomas,
Thomas Huth writes:
> Hi Nikunj,
>
> On Wed, 22 Apr 2015 16:27:20 +0530
> Nikunj A Dadhania wrote:
>
>> PCI Enumeration has been part of SLOF. Now with hotplug code addition
>> in Qemu, it makes more sense to have this code a one place, i.e. Qemu.
>
> s/Qemu/QEMU/ and s/code a one p
Thomas Huth writes:
> On Fri, 24 Apr 2015 09:22:33 +0530
> Nikunj A Dadhania wrote:
>
>>
>> Hi Thomas,
>>
>> Thomas Huth writes:
>> > Am Wed, 22 Apr 2015 16:27:19 +0530
>> > schrieb Nikunj A Dadhania :
>> >
>> >> With the addition of 64-bit BARS and increase in the mmio address
>> >> space, t
Thomas Huth writes:
> On Fri, 24 Apr 2015 12:56:57 +0200
> Thomas Huth wrote:
>
>> On Fri, 24 Apr 2015 09:22:33 +0530
>> Nikunj A Dadhania wrote:
>>
>> >
>> > Hi Thomas,
>> >
>> > Thomas Huth writes:
>> > > Am Wed, 22 Apr 2015 16:27:19 +0530
>> > > schrieb Nikunj A Dadhania :
>> > >
>> > >>
On 2015/03/13 08:20PM, Masami Hiramatsu wrote:
> (2015/03/13 5:24), Arnaldo Carvalho de Melo wrote:
> > Em Mon, Dec 15, 2014 at 08:20:32PM +0530, Naveen N. Rao escreveu:
> >> Currently, perf probe considers patterns including a '.' to be a file.
> >> However, this causes problems on powerpc ABIv1 w
On 2015/03/12 05:23PM, Arnaldo Carvalho de Melo wrote:
> Em Mon, Dec 15, 2014 at 08:20:33PM +0530, Naveen N. Rao escreveu:
> > If using the symbol table, symbol addresses are not being fixed up
> > properly, resulting in probes being placed at wrong addresses:
> >
> > # perf probe do_fork
> >
On 2015/03/12 05:30PM, Arnaldo Carvalho de Melo wrote:
> Em Mon, Dec 15, 2014 at 08:20:35PM +0530, Naveen N. Rao escreveu:
> > Allow perf probe to work on powerpc ABIv1 without the need to specify
> > the leading dot '.' for functions. 'perf probe do_fork' works with this
> > patch.
> >
> > Introd
On 2015/03/13 08:20PM, Masami Hiramatsu wrote:
> (2015/03/13 5:24), Arnaldo Carvalho de Melo wrote:
> > Em Mon, Dec 15, 2014 at 08:20:32PM +0530, Naveen N. Rao escreveu:
> >> Currently, perf probe considers patterns including a '.' to be a file.
> >> However, this causes problems on powerpc ABIv1 w
Thomas Huth writes:
> On Fri, 24 Apr 2015 12:56:57 +0200
> Thomas Huth wrote:
>
>> On Fri, 24 Apr 2015 09:22:33 +0530
>> Nikunj A Dadhania wrote:
>>
>> >
>> > Hi Thomas,
>> >
>> > Thomas Huth writes:
>> > > Am Wed, 22 Apr 2015 16:27:19 +0530
>> > > schrieb Nikunj A Dadhania :
>> > >
>> > >>
Currently, PowerPC PowerNV platform utilizes ppc_md.pcibios_fixup(),
which is called for once after PCI probing and resource assignment
are completed, to allocate platform required resources for PCI devices:
PE#, IO and MMIO mapping, DMA address translation (TCE) table etc.
Obviously, it's not hotp
The series of patches intend to support PCI slot for PowerPC PowerNV platform,
which is running on top of skiboot firmware. The patchset requires corresponding
changes from skiboot firmware, which is sent to skib...@lists.ozlabs.org for
review. The PCI slots are exposed by skiboot with device node
The patch enables M64 window on P7IOC, which has been enabled on
PHB3. Comparing to PHB3, there are 16 M64 BARs and each of them
are divided to 8 segments. So each PHB can support 128 M64 segments.
Also, P7IOC has M64DT, which helps mapping one particular M64
segment# to arbitrary PE#. However, we
The PHB's IO or M32 window is divided evenly to segments, each of
them can be mapped to arbitrary PE# by IODT or M32DT. Current code
figures out the consumed IO and M32 segments by one particular PE
from the windows of the PE's upstream bridge. It won't be reliable
once we extend M64 windows of roo
We're having the hardware or enforced (on P7IOC) limitation: M64
segment#x can only be assigned to PE#x. IO and M32 segment can be
mapped to arbitrary PE# via IODT and M32DT. It means the PE number
should be x if M64 segment#x has been assigned to the PE. Also, each
PE own one M64 segment at most.
The pci_dn instances are allocated from memblock or bootmem when
creating PCI controller (hoses) in setup_arch(). The PCI hotplug,
which will be supported by proceeding patches, will release PCI
device nodes and their corresponding pci_dn on unplugging event.
The pci_dn instance memory chunks alloe
The patch exports 3 functions, which base on corresponding OPAL
APIs to get or set PCI slot status. Those functions are going to
be used by PCI hotplug module in subsequent patches:
pnv_pci_get_presence_status() opal_pci_get_presence_status()
pnv_pci_get_power_status() opal_pci_get_powe
The original code doesn't support releasing PEs dynamically, meaning
that PE and the associated resources (IO, M32, M64 and DMA) can't
be released when unplugging a PCI adapter from one hotpluggable slot.
The patch takes object oriented methodology, introducs reference
count to PE, which is initia
Nobody is using the this function. The patch drops it.
Signed-off-by: Gavin Shan
---
arch/powerpc/platforms/powernv/pci-ioda.c | 71 ---
1 file changed, 71 deletions(-)
diff --git a/arch/powerpc/platforms/powernv/pci-ioda.c
b/arch/powerpc/platforms/powernv/pci-ioda.
Currently, the PEs and their associated resources are assigned
in ppc_md.pcibios_fixup(). The function is called for once after
PCI probing and resources assignment are finished. Obviously, it's
not hotplug friendly. The patch creates PEs dynamically by
ppc_md.pcibios_setup_bridge(), which is calle
During the PCI plugging event, the PCI devices are rescanned and
their IO and MMIO resources are reassigned. However, the PowerNV
platform will assign PE# based on that, which depends on updating
to window of bridge of the PE's primary bus.
The patch updates the windows of bridge of PE's primary b
In hotplug case, function pcibios_add_pci_devices() is called to
rescan the specified PCI bus, which might not have any child devices.
Access to the PCI bus's child device node will cause kernel crash
without exception. The patch adds condition of skipping scanning
PCI bus without child devices, in
The patch intends to add standalone driver to support PCI hotplug
for PowerPC PowerNV platform, which runs on top of skiboot firmware.
The firmware identified hotpluggable slots and marked their device
tree node with proper "ibm,slot-pluggable" and "ibm,reset-by-firmware".
The driver simply scans d
For P7IOC, the whole available DMA32 space, which is below the
MEM32 space, is evenly divided into 256MB segments. How many
continuous segments assigned to one particular PE depends on
the PE's DMA weight that is figured out from the type of each
PCI devices contained in the PE, and PHB's DMA weigh
Function pnv_pci_reset_secondary_bus() is used to reset specified
PCI bus, which is leaded by root complex or PCI bridge. That means
the function shouldn't be called on PCI root bus and the patch
removes the logic for that case.
Also, some adapters beneath the indicated PCI bus may require
fundame
Commit 1c509148b ("powerpc/eeh: Do probe on pci_dn") probes EEH
devices in early stage, which is reasonable to pSeries platform.
However, it's wrong for PowerNV platform because the PE# isn't
determined until the resources (IO and MMIO) are assigned to
PE. So we have to delay probing EEH devices fo
For PowerNV platform, running on top of skiboot, all PE level reset
should be routed to firmware if the bridge of the PE primary bus has
device-node property "ibm,reset-by-firmware". Otherwise, the kernel
has to issue hot reset on PE's primary bus despite the requested reset
types, which is the beh
We might not get some PCI slot information (e.g. power status)
immediately by OPAL API. Instead, opal_pci_poll() need to be called
for the required information.
The patch introduces pnv_pci_poll(), which bases on original
pnv_eeh_poll(), to cover the above case
Signed-off-by: Gavin Shan
---
arc
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