Hi Peter,
Peter Zijlstra writes:
> On Tue, Mar 14, 2017 at 02:31:51PM +0530, Madhavan Srinivasan wrote:
>
>> >Huh? PPC hasn't yet implemented this? Then why are you fixing it?
>>
>> yes, PPC hasn't implemented this (until now).
>
> until now where?
On powerpc there is currently no kernel suppor
Arnd Bergmann writes:
> On Tue, Mar 14, 2017 at 11:51 AM, Michael Ellerman
> wrote:
>> Michael Ellerman writes:
>>
>>> We'd like to eventually remove NO_IRQ on powerpc, so remove usages of it
>>> from electra_cf.c which is a powerpc-only driver.
>>>
>>> Signed-off-by: Michael Ellerman
>>> ---
On Tue, Mar 14, 2017 at 03:05:27PM -0600, Alex Williamson wrote:
> On Fri, 10 Mar 2017 14:53:37 +1100
> Alexey Kardashevskiy wrote:
>
> > This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE_INDIRECT
> > and H_STUFF_TCE requests targeted an IOMMU TCE table used for VFIO
> > without passing
Geert Uytterhoeven writes:
> Submitters of device tree binding documentation may forget to CC
> the subsystem maintainer if this is missing.
>
> Signed-off-by: Geert Uytterhoeven
> Cc: Benjamin Herrenschmidt
> Cc: Paul Mackerras
> Cc: Michael Ellerman
> Cc: linuxppc-dev@lists.ozlabs.org
> ---
Thorsten Leemhuis writes:
> Hi! Find below my first regression report for Linux 4.11. It lists 9
> regressions I'm currently aware of.
>
> As always: Are you aware of any other regressions? Then please let me
> know (simply CC regressi...@leemhuis.info). And please tell me if there
> is anything
Chris Packham writes:
> On 15/03/17 00:57, Michael Ellerman wrote:
>> Chris Packham writes:
>>> On 13/03/17 21:52, Chandan Rajendra wrote:
On Monday, March 13, 2017 03:33:07 AM Chris Packham wrote:
> I've just attempted to build a powerpc kernel from 4.11-rc2 using a
> custom defcon
On Tue, 14 Mar 2017, Chris Metcalf wrote:
> On 3/14/2017 12:12 PM, Till Smejkal wrote:
> > On Mon, 13 Mar 2017, Andy Lutomirski wrote:
> > > On Mon, Mar 13, 2017 at 7:07 PM, Till Smejkal
> > > wrote:
> > > > On Mon, 13 Mar 2017, Andy Lutomirski wrote:
> > > > > This sounds rather complicated. Get
On 3/14/2017 12:12 PM, Till Smejkal wrote:
On Mon, 13 Mar 2017, Andy Lutomirski wrote:
On Mon, Mar 13, 2017 at 7:07 PM, Till Smejkal
wrote:
On Mon, 13 Mar 2017, Andy Lutomirski wrote:
This sounds rather complicated. Getting TLB flushing right seems
tricky. Why not just map the same thing in
On Tue, 14 Mar 2017, David Laight wrote:
> From: Linuxppc-dev Till Smejkal
> > Sent: 13 March 2017 22:14
> > The only way until now to create a new memory map was via the exported
> > function 'mm_alloc'. Unfortunately, this function not only allocates a new
> > memory map, but also completely init
On Mon, 13 Mar 2017, Andy Lutomirski wrote:
> On Mon, Mar 13, 2017 at 7:07 PM, Till Smejkal
> wrote:
> > On Mon, 13 Mar 2017, Andy Lutomirski wrote:
> >> This sounds rather complicated. Getting TLB flushing right seems
> >> tricky. Why not just map the same thing into multiple mms?
> >
> > This
On Fri, 10 Mar 2017 14:53:37 +1100
Alexey Kardashevskiy wrote:
> This allows the host kernel to handle H_PUT_TCE, H_PUT_TCE_INDIRECT
> and H_STUFF_TCE requests targeted an IOMMU TCE table used for VFIO
> without passing them to user space which saves time on switching
> to user space and back.
>
On 03/13/2017 03:29 AM, Bharata B Rao wrote:
> On Thu, Mar 09, 2017 at 01:34:00PM -0800, Tyrel Datwyler wrote:
>> On 03/08/2017 08:37 PM, Bharata B Rao wrote:
>>> The following warning is seen when a CPU is hot unplugged on a PowerKVM
>>> guest:
>>
>> Is this the case with cpus present at boot? Wha
On Fri, 10 Mar 2017 14:53:31 +1100
Alexey Kardashevskiy wrote:
> So far iommu_table obejcts were only used in virtual mode and had
> a single owner. We are going to change this by implementing in-kernel
> acceleration of DMA mapping requests. The proposed acceleration
> will handle requests in re
On 15/03/17 00:57, Michael Ellerman wrote:
> Chris Packham writes:
>
>> On 13/03/17 21:52, Chandan Rajendra wrote:
>>> On Monday, March 13, 2017 03:33:07 AM Chris Packham wrote:
Hi,
I've just attempted to build a powerpc kernel from 4.11-rc2 using a
custom defconfig (available
On Tue, Mar 14, 2017 at 3:02 AM, Thorsten Leemhuis
wrote:
>
> Desc: PowerPC crashes on boot, bisected to commit 5657933dbb6e
> Repo: 2017-03-02
> https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1343553.html
> Stat: 2017-03-09
> https://www.mail-archive.com/linux-kernel@vger.kernel.o
linux into perf/core
(2017-03-07 08:14:14 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux.git
tags/perf-core-for-mingo-4.12-20170314
for you to fetch changes up to 5f6bee34707973ea7879a7857fd63ddccc92fff3:
kprobe
From: "Naveen N. Rao"
We indicate support for accepting sym+offset with kretprobes through a
line in ftrace README. Parse the same to identify support and choose the
appropriate format for kprobe_events.
As an example, without this perf patch, but with the ftrace changes:
naveen@ubuntu:~/linu
From: "Naveen N. Rao"
Simplify and separate out the ftrace README scanning logic into a
separate helper. This is used subsequently to scan for all patterns of
interest and to cache the result.
Since we are only interested in availability of probe argument type x,
we will only scan for that.
Sig
From: "Naveen N. Rao"
perf now uses an offset from _text/_stext for kretprobes if the kernel
supports it, rather than the actual function name. As such, let's choose
the LEP for powerpc ABIv2 so as to ensure the probe gets hit. Do it only
if the kernel supports specifying offsets with kretprobes.
On Fri, 10 Mar 2017 14:53:30 +1100
Alexey Kardashevskiy wrote:
> At the moment iommu_table can be disposed by either calling
> iommu_table_free() directly or it_ops::free(); the only implementation
> of free() is in IODA2 - pnv_ioda2_table_free() - and it calls
> iommu_table_free() anyway.
>
> A
On Tue, 14 Mar 2017 11:55:33 +1100
David Gibson wrote:
> On Tue, Mar 14, 2017 at 11:54:03AM +1100, Alexey Kardashevskiy wrote:
> > On 10/03/17 15:48, David Gibson wrote:
> > > On Fri, Mar 10, 2017 at 02:53:27PM +1100, Alexey Kardashevskiy wrote:
> > >> This is my current queue of patches to a
On Tue, 2017-03-14 at 12:29 +, Reshetova, Elena wrote:
> > Elena Reshetova writes:
> >
> > > refcount_t type and corresponding API should be
> > > used instead of atomic_t when the variable is used as
> > > a reference counter. This allows to avoid accidental
> > > refcounter overflows that m
On Mon, 13 Mar 2017 11:31:28 +0530
"Gautham R. Shenoy" wrote:
> From: "Gautham R. Shenoy"
>
> POWER9 platform can be configured to rebalance per-thread resources
> within a core in order to improve SMT performance. Certain STOP
> states can be configure to relinquish resources include some
> h
On Mon, 13 Mar 2017 11:31:27 +0530
"Gautham R. Shenoy" wrote:
> From: "Gautham R. Shenoy"
>
> Currently during idle-init on power9, if we don't find suitable stop
> states in the device tree that can be used as the
> default_stop/deepest_stop, we set stop0 (ESL=1,EC=1) as the default
> stop sta
> Elena Reshetova writes:
>
> > refcount_t type and corresponding API should be
> > used instead of atomic_t when the variable is used as
> > a reference counter. This allows to avoid accidental
> > refcounter overflows that might lead to use-after-free
> > situations.
> >
> > Signed-off-by: Elen
On Mon, 13 Mar 2017 11:31:26 +0530
"Gautham R. Shenoy" wrote:
> [Changelog written with inputs from sva...@linux.vnet.ibm.com]
> Signed-off-by: Gautham R. Shenoy
Reviewed-by: Nicholas Piggin
> ---
> arch/powerpc/platforms/powernv/smp.c | 10 +-
> 1 file changed, 9 insertions(+), 1 de
Em Thu, Mar 09, 2017 at 05:37:38PM +1100, Michael Ellerman escreveu:
> "Naveen N. Rao" writes:
> > On 2017/03/08 11:29AM, Arnaldo Carvalho de Melo wrote:
> >> > I wasn't sure if you were planning on picking up KPROBES_ON_FTRACE for
> >> > v4.11. If so, it would be good to take this patch through
On Tue, Mar 14, 2017 at 02:31:51PM +0530, Madhavan Srinivasan wrote:
> >Huh? PPC hasn't yet implemented this? Then why are you fixing it?
>
> yes, PPC hasn't implemented this (until now).
until now where?
> And did not understand "Then why are you fixing it?"
I see no implementation; so why ar
On Tue, Mar 14, 2017 at 11:51 AM, Michael Ellerman wrote:
> Michael Ellerman writes:
>
>> We'd like to eventually remove NO_IRQ on powerpc, so remove usages of it
>> from electra_cf.c which is a powerpc-only driver.
>>
>> Signed-off-by: Michael Ellerman
>> ---
>> drivers/pcmcia/electra_cf.c | 4
On 02/20/2017 11:41 PM, Alexey Kardashevskiy wrote:
Cc: Gavin Shan
Signed-off-by: Alexey Kardashevskiy
Tested-by: Mauricio Faria de Oliveira
P.S.: sorry, late, but for the record.
--
Mauricio Faria de Oliveira
IBM Linux Technology Center
POWER8 uses bit 36 in SRR1 like POWER9 for i-side machine checks, and
contains several conditions for link timeouts that are not currently
handled.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce_power.c | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
Move the handling (corrective action) of machine checks to the table
based evaluation.
This changes P7 and P8 ERAT flushing from using SLB flush to using ERAT
flush.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce_power.c | 328 +---
1 file changed
Have machine types define i-side and d-side tables to describe their
machine check encodings, and match entries to evaluate (for reporting)
machine checks.
Functionality is mostly unchanged (tested with a userspace harness), but
it does make a change in that it no longer records DAR as the effecti
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/mce.h | 91
arch/powerpc/kernel/mce_power.c | 92 +
2 files changed, 92 insertions(+), 91 deletions(-)
diff --git a/arch/powerpc/include/asm/mce.h b/arch/
Use the flush function introduced with the POWER9 machine check handler
for POWER7 and 8, rather than open coding it multiple times in callers.
There is a specific ERAT flush type introduced for POWER9, but the
POWER7-8 ERAT errors continue to do SLB flushing (which also flushes
ERAT), so as not t
Print the faulting address of the machine check that may help with
debugging. The effective address reported can be a target memory address
rather than the faulting instruction address.
Fix up a dangling bracket while here.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/mce.c | 3 ++-
1
Hi,
This is a rebase of the table based MCE patches on top of the POWER9
handler that was merged upstream. Plus a couple of misc things (patches
1 and 6).
The plan is to have OPAL firmware do most of this recovery and parsing
in future, but I think it's worth tidying this up. IMO it's easier to
s
Elena Reshetova writes:
> refcount_t type and corresponding API should be
> used instead of atomic_t when the variable is used as
> a reference counter. This allows to avoid accidental
> refcounter overflows that might lead to use-after-free
> situations.
>
> Signed-off-by: Elena Reshetova
> Sig
Chris Packham writes:
> On 13/03/17 21:52, Chandan Rajendra wrote:
>> On Monday, March 13, 2017 03:33:07 AM Chris Packham wrote:
>>> Hi,
>>>
>>> I've just attempted to build a powerpc kernel from 4.11-rc2 using a
>>> custom defconfig (available on request) and I'm hitting the following
>>> error
On Fri, 2017-03-10 at 02:33:51 UTC, Larry Finger wrote:
> Code inserted during the code merged between kernels 4.10 and 4.11-rc1
> caused an early panic quickly followed by a complete shutdown for
> PowerPC. The traceback was not displayed long enough to read or
> photograph, thus it is not reprodu
On Tue, 2017-03-07 at 23:40:21 UTC, Michael Ellerman wrote:
> Recent toolchains force the TOC to be 256 byte aligned. We need to
> enforce this alignment in the zImage linker script, otherwise pointers
> to our TOC variables (__toc_start) could be incorrect. If the actual
> start of the TOC and __t
On Tue, 2017-03-07 at 00:39:31 UTC, Cyril Bur wrote:
> On POWER8 (ISA 2.07) lxvx and stxvx are defined to be extended mnemonics
> of lxvd2x and stxvd2x. For POWER9 (ISA 3.0) the HW architects in their
> infinite wisdom made lxvx and stxvx instructions in their own right.
>
> POWER9 aware GCC will
On Tue, 2017-02-28 at 02:00:46 UTC, Nicholas Piggin wrote:
> A synchronous machine check is an exception raised by the attempt to
> execute the current instruction. If the error can't be corrected, it
> can make sense to SIGBUS the currently running process.
>
> In other cases, the error condition
On Wed, 2017-02-22 at 04:43:59 UTC, Alexey Kardashevskiy wrote:
> The IODA2 specification says that a 64 DMA address cannot use top 4 bits
> (3 are reserved and one is a "TVE select"); bottom page_shift bits
> cannot be used for multilevel table addressing either.
>
> The existing IODA2 table allo
On Tue, 2017-02-21 at 02:41:31 UTC, Alexey Kardashevskiy wrote:
> On POWERNV platform, in order to do DMA via IOMMU (i.e. 32bit DMA in
> our case), a device needs an iommu_table pointer set via
> set_iommu_table_base().
>
> The codeflow is:
> - pnv_pci_ioda2_setup_dma_pe()
> - pnv_pci_ioda2_
On Mon, 2017-02-20 at 13:59:03 UTC, Madhavan Srinivasan wrote:
> MMCRA[SDAR_MODE] specifices how the SDAR should be updated in
> continous sampling mode. On P9 it must be set to 0b00 when
> MMCRA[63] is set.
>
> Fixes: c7c3f568beff2 ('powerpc/perf: macros for power9 format encoding')
> Signed-off-
On Mon, 2017-02-20 at 13:56:30 UTC, Madhavan Srinivasan wrote:
> Power9 DD1 do not support PMU_HAS_SIER flag and sdsync
> in perf_get_data_addr() defaults to MMCRA_SDSYNC which
> is wrong. Since power9 MMCRA does not support SDSYNC bit,
> patch includes PPMU_NO_SIAR flag to the check and set the
>
Adding Pradipta and Christy.
Harshal Patil
E-mail: harshal.pa...@in.ibm.com
- Original message -From: Harshal Patil/India/IBMTo: linuxppc-dev@lists.ozlabs.orgCc: Sudipto Ghosh/India/IBM@IBMINSubject: ioctl structs differ from x86_64?Date: Tue, Mar 14, 2017 4:07 PM
Hello,
I am looking
Hello,
I am looking into a bug, https://bugzilla.linux.ibm.com/show_bug.cgi?id=152493 ( external mirror is at, https://github.com/opencontainers/runc/issues/1364)
Recently in runc code, they added this code https://github.com/opencontainers/runc/commit/eea28f480db435dbef4a275de9776b9934818b8c#
From: Linuxppc-dev Till Smejkal
> Sent: 13 March 2017 22:14
> The only way until now to create a new memory map was via the exported
> function 'mm_alloc'. Unfortunately, this function not only allocates a new
> memory map, but also completely initializes it. However, with the
> introduction of fir
The mm_struct corresponding to the current task is acquired each time
an interrupt is raised. So to simplify the code, we only get the
mm_struct when attaching an AFU context to the process.
The mm_count reference is increased to ensure that the mm_struct can't
be freed. The mm_struct will be relea
The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translation Fault Handling
- CAPP
- Memory Context ID
If a val
Rename a few functions, changing the '_psl' suffix to '_psl8', to make
clear that the implementation is psl8 specific.
Those functions will have an equivalent implementation for the psl9 in
a later patch.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/cxl.h | 22 ++---
This series adds support for a cxl card which supports the Coherent
Accelerator Interface Architecture 2.0.
It requires IBM Power9 system and the Power Service Layer, version 9.
The PSL provides the address translation and system memory cache for
CAIA compliant Accelerators.
the PSL attaches to th
Point out the specific Coherent Accelerator Interface Architecture,
level 1, registers.
Code and functions specific to PSL8 (CAIA1) must be framed.
Signed-off-by: Christophe Lombard
---
drivers/misc/cxl/context.c | 28 +++-
drivers/misc/cxl/cxl.h | 35 +++-
The service layer API (in cxl.h) lists some low-level functions whose
implementation is different on PSL8, PSL9 and XSL:
- Init implementation for the adapter and the afu.
- Invalidate TLB/SLB.
- Attach process for dedicated/directed models.
- Handle psl interrupts.
- Debug registers for the adapte
The two fields pid and tid of the structure cxl_irq_info are only used
in the guest environment. To avoid confusion, it's not necessary
to fill the fields in the bare-metal environment.
The PSL Process and Thread Identification Register is only used when
attaching a dedicated process for PSL8 only.
Michael Ellerman writes:
> We'd like to eventually remove NO_IRQ on powerpc, so remove usages of it
> from electra_cf.c which is a powerpc-only driver.
>
> Signed-off-by: Michael Ellerman
> ---
> drivers/pcmcia/electra_cf.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Ping anyon
Hi! Find below my first regression report for Linux 4.11. It lists 9
regressions I'm currently aware of.
As always: Are you aware of any other regressions? Then please let me
know (simply CC regressi...@leemhuis.info). And please tell me if there
is anything in the report that shouldn't be there.
If not all threads were in winkle, full state loss recovery is not
necessary and can be avoided. A previous patch removed this optimisation
due to some complexity with the implementation. Re-implement it by
counting the number of threads in winkle with the per-core idle state.
Only restore full sta
When taking the core idle state lock, grab it immediately like a
regular lock, rather than adding more tests in there. Holding the lock
keeps it stable, so there is no need to do it whole holding the
reservation.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/idle_book3s.S | 20 +
In preparation for adding more bits to the core idle state word,
move the lock bit up, and unlock by flipping the lock bit rather
than masking off all but the thread bits.
Add branch hints for atomic operations while we're here.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/cpuidl
POWER9 does not use this field, so it should be moved into the POWER8
code. Update the documentation in the paca struct too.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/include/asm/paca.h | 12 ++--
arch/powerpc/kernel/idle_book3s.S | 13 +++--
2 files changed, 17 insertion
The ISA specifies power save wakeup can cause a machine check interrupt.
The machine check handler currently has code to handle that for POWER8,
but POWER9 crashes when trying to execute the P8 style sleep
instructions.
So queue up the machine check, then call into the idle code to wake up
as the
This reduces the number of nops for POWER8.
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/idle_book3s.S | 19 ---
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/arch/powerpc/kernel/idle_book3s.S
b/arch/powerpc/kernel/idle_book3s.S
index 405631b2c229..928
The POWER8 idle code has a neat trick of programming the power on engine
to restore a low bit into HSPRG0, so idle wakeup code can test and see
if it has been programmed this way and therefore lost all state, and
avoiding the expensive full restore if not.
However this messes with our r13 PACA poi
Should be no functional change.
Reviewed-by: Gautham R. Shenoy
Signed-off-by: Nicholas Piggin
---
arch/powerpc/kernel/exceptions-64s.S | 26 +---
arch/powerpc/kernel/idle_book3s.S| 76
2 files changed, 51 insertions(+), 51 deletions(-)
diff --gi
Hi,
This is a resend of the previous idle series, with the addition that
I accounted for Gautham's feedback, and also re-introduced the feature
to avoid full state restore by counting winkles rather than special
HSPRG0 bit.
The two big things we get from this, is no longer messing with HSPRG0
in
On Monday 13 March 2017 06:20 PM, Peter Zijlstra wrote:
On Mon, Mar 13, 2017 at 04:45:51PM +0530, Madhavan Srinivasan wrote:
- should you not have fixed this in the tool only? This patch
effectively breaks ABI on big-endian architectures.
IIUC, we are the first BE user for this feature
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