ements the WDIOC_SETTIMEOUT ioctl.
Signed-off-by: Christophe Leroy
diff -ur linux-3.7.7/drivers/watchdog/mpc8xxx_wdt.c
linux/drivers/watchdog/mpc8xxx_wdt.c
--- linux-3.7.7/drivers/watchdog/mpc8xxx_wdt.c 2013-02-11 18:05:09.0
+0100
+++ linux/drivers/watchdog/mpc8xxx_wdt.c2013-0
ario-bank-c";
reg = <0x960 0x10>;
interrupts = <255 255 255 255 1 2 6 9 10 11 14 15 23 24 26 31>;
interrupt-parent = <&CPM_PIC>;
gpio-controller;
};
Signed-off-by: Christophe Leroy
diff -ur linux-3.7.9/
allows to set up the userspace timeout.
The driver also implements the WDIOC_SETTIMEOUT ioctl.
Signed-off-by: Christophe Leroy
diff -ur linux-3.7.9/drivers/watchdog/mpc8xxx_wdt.c
linux/drivers/watchdog/mpc8xxx_wdt.c
--- linux-3.7.9/drivers/watchdog/mpc8xxx_wdt.c 2013-02-17 19:53:32.0
+0
irq_eoi() is already called by generic_handle_irq() so
it shall not be called a again
Signed-off-by: Christophe Leroy
Index: linux/arch/powerpc/platforms/8xx/m8xx_setup.c
===
--- linux/arch/powerpc/platforms/8xx/m8xx_setup.c
irq_eoi() is already called by generic_handle_irq() so
it shall not be called a again
Signed-off-by: Christophe Leroy
Index: linux/arch/powerpc/platforms/8xx/m8xx_setup.c
===
--- linux/arch/powerpc/platforms/8xx/m8xx_setup.c
t 300 bauds.
This fix limits to one byte the waiting period.
Signed-off-by: Christophe Leroy
--- linux-3.5-vanilla/drivers/tty/serial/cpm_uart/cpm_uart_core.c
2012-07-21 22:58:29.0 +0200
+++ linux-3.5/drivers/tty/serial/cpm_uart/cpm_uart_core.c 2012-08-09
17:38:37.0
Hello,
I'm not sure who to address this Patch to.
It fixes a desynchronisation problem with CPM UART driver on Powerpc MPC8xx.
The problem happens if data is received before the device is open by the user
application.
Signed-off-by: Christophe Leroy
--- linux-3.5-vanilla/drivers/tty/s
This patch fixes a desynchronisation problem with CPM UART driver on
Powerpc MPC8xx. The problem happens if data is received before the device
is open by the user application.
Signed-off-by: Christophe Leroy
--- linux-3.5-vanilla/drivers/tty/serial/cpm_uart/cpm_uart_core.c
2012-07-21 22
Setting the fifo to only 1 byte generates one interrupt every 1ms at 9600 bauds.
This is too much. This patch reduces the threshold to speeds below 2400 bauds
like in the 8250 UART driver.
Signed-off-by: Christophe Leroy
--- linux-3.5-vanilla/drivers/tty/serial/cpm_uart/cpm_uart_core.c
maxidl register was set to fifo size. There is no reason to set this
register to same value as fifo size. Setting it now to 0x10 by default
as in the UCC UART driver.
Signed-off-by: Christophe Leroy
--- linux-3.5-vanilla/drivers/tty/serial/cpm_uart/cpm_uart_core.c
2012-07-21 22:58
UART.
Signed-off-by: Christophe Leroy
--- linux-3.5-vanilla/drivers/tty/serial/cpm_uart/cpm_uart_core.c
2012-07-21 22:58:29.0 +0200
+++ linux-3.5/drivers/tty/serial/cpm_uart/cpm_uart_core.c 2012-08-09
17:38:37.0 +0200
@@ -501,6 +501,7 @@
struct uart_cpm_port
out' allows to set up the userspace timeout.
This patch also adds the WDIOC_SETTIMEOUT ioctl to the driver.
Signed-off-by: Christophe Leroy
--- linux-3.8.13/drivers/watchdog/mpc8xxx_wdt.c 2013-05-11 22:57:46.0
+0200
+++ linux/drivers/watchdog/mpc8xxx_wdt.c2013-08-08 02:12:15.000
cpm_uart serial driver uses GPIO for control signals. In order to be used
properly, GPIOs have to be reserved. Comment in gpiolib.c considers illegal
the use of GPIOs without requesting them. In addition, the direction of the
GPIO has to be set properly.
Signed-off-by: Christophe Leroy
diff -ur
.
The new message tries to be more generic in order to make the user understand
that the Oops is due to something wrong with an instruction, not necessarily
due to an FPU instruction.
Signed-off-by: Christophe Leroy
diff -ur linux-3.11-rc6/arch/powerpc/kernel/traps.c
linux/arch/powerpc/kernel
8xx.
Signed-off-by: Christophe Leroy
diff -ur linux-3.11.org/arch/powerpc/mm/pgtable.c
linux-3.11/arch/powerpc/mm/pgtable.c
--- linux-3.11.org/arch/powerpc/mm/pgtable.c2013-09-02 22:46:10.0
+0200
+++ linux-3.11/arch/powerpc/mm/pgtable.c2013-09-09 11:25:57.0
+0200
Activating CONFIG_PIN_TLB is supposed to pin the IMMR and the first three
8Mbytes pages. But the setting of the MD_CTR was missing so as the index is
decremented every DTLB update, the pinning of the third 8Mbytes page was
overwriting the DTLB entry for IMMR.
Signed-off-by: Christophe Leroy
8xx.
Signed-off-by: Christophe Leroy
diff -ur linux-3.11.org/arch/powerpc/mm/pgtable.c
linux-3.11/arch/powerpc/mm/pgtable.c
--- linux-3.11.org/arch/powerpc/mm/pgtable.c2013-09-02 22:46:10.0
+0200
+++ linux-3.11/arch/powerpc/mm/pgtable.c2013-09-09 11:25:57.0
+0200
This is a reorganisation of the setup of the TLB at kernel startup, in order
to handle the CONFIG_PIN_TLB case in accordance with chapter 8.10.3 of MPC866
and MPC885 reference manuals.
Signed-off-by: Christophe Leroy
diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S
linux-3.11/arch
written
being entry 31, next entries would possibly get overwritten after.
We are now starting from entry 31 and decrementing.
Signed-off-by: Christophe Leroy
diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S
linux-3.11/arch/powerpc/kernel/head_8xx.S
--- linux-3.11.org/arch/powerpc/kernel
not pinned.
Signed-off-by: Christophe Leroy
diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S
linux-3.11/arch/powerpc/kernel/head_8xx.S
--- linux-3.11.org/arch/powerpc/kernel/head_8xx.S 2013-09-02
22:46:10.0 +0200
+++ linux-3.11/arch/powerpc/kernel/head_8xx.S 2013-09-09 11
Signed-off-by: Christophe Leroy
diff -ur linux-3.11.org/arch/powerpc/kernel/head_8xx.S
linux-3.11/arch/powerpc/kernel/head_8xx.S
--- linux-3.11.org/arch/powerpc/mm/init_32.c2013-09-02 22:46:10.0
+0200
+++ linux-3.11/arch/powerpc/mm/init_32.c2013-09-09 11:28:54.00
: self tests passed, processed 225944 bytes in 3289576 nsec
Signed-off-by: Christophe Leroy
Index: a/lib/Kconfig
===
--- a/lib/Kconfig (révision 5325)
+++ b/lib/Kconfig (copie de travail)
@@ -102,6 +102,7 @@
choice
Commit beb2dc0a7a84be003ce54e98b95d65cc66e6e536 breaks the MPC8xx which seems
to not support using mfspr SPRN_TBRx instead of mftb/mftbu despite
what is written in the reference manual
This patchs revert to the use of mftb/mftbu when CONFIG_8xx is selected
Signed-off-by: Christophe Leroy
diff
: self tests passed, processed 225944 bytes in 3289576 nsec
Signed-off-by: Christophe Leroy
diff -ur a/arch/powerpc/configs/adder875_defconfig
b/arch/powerpc/configs.new/adder875_defconfig
--- a/arch/powerpc/configs/adder875_defconfig 2013-11-22 18:20:10.342968268
+0100
+++ b/arch/powerpc
t;big" kernels
(for instance when activating CONFIG_LOCKDEP_SUPPORT) without having
to activate CONFIG_PIN_TLB.
Signed-off-by: Christophe Leroy
diff -ur a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
Convert mpc8xxx_wdt.c to the new watchdog API.
Signed-off-by: Christophe Leroy
diff -ur a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
--- a/drivers/watchdog/mpc8xxx_wdt.c2013-05-11 22:57:46.0 +0200
+++ b/drivers/watchdog/mpc8xxx_wdt.c2013-11-30 16:14
MPC8xx watchdog is enabled at startup by HW.
If the bootloader disables it, it cannot be reenabled.
Signed-off-by: Christophe Leroy
diff -ur a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
--- a/drivers/watchdog/mpc8xxx_wdt.c2013-05-11 22:57:46.0 +0200
+++ b
Convert mpc8xxx_wdt.c to the new watchdog API.
Signed-off-by: Christophe Leroy
diff -ur a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
--- a/drivers/watchdog/mpc8xxx_wdt.c2013-05-11 22:57:46.0 +0200
+++ b/drivers/watchdog/mpc8xxx_wdt.c2013-11-30 16:14
Convert mpc8xxx_wdt.c to the new watchdog API.
Signed-off-by: Christophe Leroy
diff -ur a/drivers/watchdog/mpc8xxx_wdt.c b/drivers/watchdog/mpc8xxx_wdt.c
--- a/drivers/watchdog/mpc8xxx_wdt.c2013-05-11 22:57:46.0 +0200
+++ b/drivers/watchdog/mpc8xxx_wdt.c2013-11-30 16:14
Le 06/12/2013 20:09, Scott Wood a écrit :
On Wed, 2013-11-27 at 12:04 +0100, Christophe Leroy wrote:
Today, the only way to load kernels whose size is greater than 8Mbytes is to
activate CONFIG_PIN_TLB. Otherwise, the physical memory initially mapped is
limited to 8Mbytes. This patch sets up
CONFIG_PIN_TLB
is active or not. It allows to load "big" kernels (for instance when activating
CONFIG_LOCKDEP_SUPPORT) without having to activate CONFIG_PIN_TLB.
Signed-off-by: Christophe Leroy
diff -ur a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
--- a/arch/powerpc/Kconfig
+++ b/ar
given to the kernel through register r7.
This is done regardless of whether CONFIG_PIN_TLB is active or not. It allows to
load "big" kernels (for instance when activating CONFIG_LOCKDEP_SUPPORT) without
having to activate CONFIG_PIN_TLB.
Not-yet-signed-off-by: Christophe Leroy
Index: lin
This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
Unlike PPC64, PPC32 doesn't provide the PACA register. Therefore the
implementation is similar to the one done in the IA64 architecture.
It is based on additional information added to the Task Info structure.
Signed-off-by: Chris
This patch provides VIRT_CPU_ACCOUTING to PPC32 architecture.
Unlike PPC64, PPC32 doesn't use the PACA convention. Therefore the
implementation is taken from the IA64 architecture.
It is based on additional information added to the Task Info structure.
Signed-off-by: Christophe Leroy
Ind
rypto operations, not the combined
authentication/encryption ones.
Note that it has been tested on MPC885, but not on MPC82xx
I would be happy to receive comments and suggestions in order to improve this
first try.
Not-yet-signed-off-by: Christophe Leroy
Index: b/drivers/crypto/tali
This patchset:
* provides several MMU TLB handling optimisation on MPC8xx.
* adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 17 +++--
1 files changed, 7 insertions(+), 10
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |7 +++
1 files changed, 3 insertions(+), 4 deletions
-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 104 --
1 files changed, 36 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1329c5a..3af6db1 100644
--- a/arch/powerpc/kernel
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 23 ++-
1 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/arch
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h |3 ++-
arch
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |8 ++--
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a
Lets save one cycle by aligning swapper_pg_dir on 16 bits boundary.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 13 +
1 files changed, 5 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 44
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29 ++---
1 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/arch
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 30 +-
1 files changed, 13 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/kernel
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |8 +---
1 files changed, 5 insertions(+), 3
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29 -
1 files changed, 16 insertions(+
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable-ppc32.h | 21 +
arch/powerpc/include/asm/pte-8xx.h |7 +--
arch/powerpc/kernel/head_8xx.S |
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 19
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S |4
3 files changed, 7 insertions(+), 1 deletions(-)
diff
implementing a 16 bit alignment of
the
PGDIR. It is not worth potentially wasting up to 64k of memory just for
removing one
instruction (ori).
2) I managed to preserve r11 while calculating the level 2 address, therefore
no more need to save r11 into CR.
Signed-off-by: Christophe Leroy
Tested
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/reg.h |3 ++-
arch
-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 104 --
1 files changed, 36 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1329c5a..3af6db1 100644
--- a/arch/powerpc/kernel
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 17 +++--
1 files changed, 7 insertions(+), 10
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |8 ++--
1 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/kernel
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |7 +++
1 files changed, 3 insertions(+), 4 deletions
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy
---
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S |4
3 files changed, 7 insertions(+), 1 deletions(-)
diff
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |8 +---
1 files changed, 5 insertions(+), 3
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy
---
arch/powerpc/include/asm/pgtable-ppc32.h | 21 +
arch/powerpc/include/asm/pte-8xx.h |7 +--
arch/powerpc/kernel/head_8xx.S |
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 28
1 files changed, 12 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/kernel
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 23 ++-
1 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/arch
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 30 ++
1 files changed, 18 insertions(+), 12 deletions(-)
diff --git a/arch
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 19
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 48
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy
---
arch/powerpc/kernel/head_8xx.S | 29 -
1 files changed, 16 insertions(+
Since coming 469d62be9263b92f2c3329540cbb1c076111f4f3, SPRG2 is used as a
scratch register just like SPRG0 and SPRG1. So Declare it as such and fix
the comment which is not valid anymore since that commit.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch
Exception InstructionAccess does not exist on MPC8xx. No need to branch there
from somewhere else.
Handling can be done directly in InstructionTLBError Exception.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so
-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 104 --
1 files changed, 36 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1329c5a
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, r10 is not used anymore
after FixupDAR. There is therefore no need to set it up with the value of DAR.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |7 +++
1 files
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with MPC885
Signed-off-by: Christophe Leroy
Tested-by: Christophe Leroy
---
Changes in v2:
- Patch number 10
Since commit 2321f33790a6c5b80322d907a92d5739e7521a13, dirty handling is not
handled here anymore. So we fix the comment.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |8 ++--
1 files changed, 2 insertions(+), 6
By XORing the upper part of the instruction code, we get a value that can
directly be verified with the second test and we can remove the first test.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |6 ++
1 files changed
DataAccess exception is never generated by MPC8xx so do the job directly where
it is used to avoid an unnecessary branching.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- arch/powerpc/mm/fault.c uses the vector number, so make sure it understands
the new ones
MD_TWC can only be used properly with 4k pages.
So lets calculate level 2 table index by ourselves.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- No need to save r11 in cr, we can do without modifying r11 in DataStoreTLBMiss
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 28
For PAGE size related operations, use PAGE size consts in order to be able to
use different page size in the futur.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 30 ++
1 files changed, 18
Branching takes two cycles on MPC8xx. Lets duplicate the two instructions
and avoid the branching.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch
Value 0x00f0 is used to force bits in TLB level 2 entry. This value is linked
to the page size and will vary when we change the page size. Lets define a const
for it in order to have it at only one place.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch
In DTLBError handler there is not need to restore r10, r11 and cr registers
after fixing DAR as they are saved again to the same place just after.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |4 ++--
1 files changed, 2
Use M_TW instead of M_TWB for storing Level 1 table address as M_TWB requires
4k aligned tables, which is only the case with 4k pages.
Consequently, we have to calculate the level 1 table index by ourselves.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch
r10 and r3 are only used inside FixupDAR function. So lets save them inside
that function only.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S | 27 +--
1 files changed, 13 insertions(+), 14 deletions
This patch activates the handling of 16k pages on the MPC8xx.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/Kconfig |2 +-
arch/powerpc/include/asm/mmu-8xx.h |2 ++
arch/powerpc/kernel/head_8xx.S |4
3 files
No need to re-set this bit at each TLB miss. Let's set it in the PTE.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- Removed PPC405 related macro from PPC8xx specific code
- PTE_NONE_MASK doesn't need PAGE_ACCESSED in Linux 2.6
arch/powerpc/include/a
There is not need to restore r10, r11 and cr registers at this end of ITLBmiss
handler as they are saved again to the same place in ITLBError handler we are
jumping to.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |8
When a PMD entry is valid, _PMD_PRESENT is set. Therefore, forcing that bit
during TLB loading is useless.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a
free the TLB as soon as
possible. This also has the advantage of removing some 8xx specific code from
fault.c
Signed-off-by: Christophe Leroy
---
Changes in v3:
- New
linux/arch/powerpc/kernel/head_8xx.S | 15 ++-
linux/arch/powerpc/mm/fault.c| 7 ---
2 files change
This patch hiddes that SPR address needed for CPU6 ERRATA handling in the macro.
Then we don't have to worry about this address directly in the code.
Signed-off-by: Christophe Leroy
---
Changes in v2:
- None
Changes in v3:
- None
arch/powerpc/kernel/head_8xx.S |
As we are not using anymore DAR to save registers, it is now available for
saving the r3 register used for CPU6 ERRATA handling. Therefore we can
remove the major hack which was to use memory location 0 to save r3.
Signed-off-by: Christophe Leroy
---
Changes in v3:
- New
linux/arch/powerpc
Le 17/09/2014 18:40, Scott Wood a écrit :
On Wed, 2014-09-17 at 18:36 +0200, Christophe Leroy wrote:
This patchset:
1) provides several MMU TLB handling optimisation on MPC8xx.
2) adds support of 16k pages on MPC8xx.
All changes have been successfully tested on a custom board equipped with
Le 18/09/2014 18:42, leroy christophe a écrit :
Le 18/09/2014 17:15, Joakim Tjernlund a écrit :
Christophe Leroy wrote on 2014/09/17 18:36:57:
Exception InstructionAccess does not exist on MPC8xx. No need to branch
there from somewhere else.
Handling can be done directly in
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