On Jun 16, 2008, at 7:06 PM, Benjamin Herrenschmidt wrote:
On Mon, 2008-06-16 at 10:46 -0500, Kumar Gala wrote:
The new e500mc core from Freescale is based on the e500v2 but with
the
following changes:
* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
On Jun 16, 2008, at 2:26 PM, Olof Johansson wrote:
On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata
cpu_specs[] = {
.machine_check =
On Jun 17, 2008, at 8:56 AM, Kumar Gala wrote:
On Jun 16, 2008, at 2:26 PM, Olof Johansson wrote:
On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
+ .machine_check = machine_check_e500,
+ .platform = ppc4080,
Do you really want the
On Jun 17, 2008, at 9:32 AM, Olof Johansson wrote:
On Jun 17, 2008, at 8:56 AM, Kumar Gala wrote:
On Jun 16, 2008, at 2:26 PM, Olof Johansson wrote:
On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
+ .machine_check = machine_check_e500,
+ .platform
On Jun 17, 2008, at 9:42 AM, Kumar Gala wrote:
But: since the cacheline is available in cputable, it can still be
used at runtime, so as long as the alignments are large enough,
stuff like the dcbz loops should still be OK (might need an audit
though to make sure there's nothing missed).
On Jun 17, 2008, at 10:04 AM, Olof Johansson wrote:
On Jun 17, 2008, at 9:42 AM, Kumar Gala wrote:
But: since the cacheline is available in cputable, it can still be
used at runtime, so as long as the alignments are large enough,
stuff like the dcbz loops should still be OK (might need an
The new e500mc core from Freescale is based on the e500v2 but with the
following changes:
* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
* Supports lwsync
* Doorbell Exceptions
* Hypervisor
---
In my powerpc-next tree.
arch/powerpc/kernel/cputable.c
On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
The new e500mc core from Freescale is based on the e500v2 but with the
following changes:
* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
* Supports lwsync
* Doorbell Exceptions
* Hypervisor
---
In my
On Jun 16, 2008, at 11:56 AM, Becky Bruce wrote:
On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
The new e500mc core from Freescale is based on the e500v2 but with
the
following changes:
* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
* Supports
On Jun 16, 2008, at 10:46 AM, Kumar Gala wrote:
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -1522,6 +1522,21 @@ static struct cpu_spec __initdata cpu_specs[]
= {
.machine_check = machine_check_e500,
.platform
On Mon, 2008-06-16 at 10:46 -0500, Kumar Gala wrote:
The new e500mc core from Freescale is based on the e500v2 but with the
following changes:
* Supports only the Enhanced Debug Architecture (DSRR0/1, etc)
* Floating Point
* No SPE
* Supports lwsync
^^
It supports SMP ?
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