On Mon, 2017-02-27 at 23:03 +1100, Michael Ellerman wrote:
> It took me a while to parse that.
>
> So because of the way the OPAL XICS emulation is implemented, setting
> the CPPR to DEFAULT_PRIORITY has the effect of masking all
> interrupts.
>
> That is because the OPAL code internally maps
Balbir Singh writes:
> With XICS emulation, setting the CPPR to DEFAULT_PRIORITY
^
(Current Processor Priority Register)
> masks all interrupts including
With XICS emulation, setting the CPPR to DEFAULT_PRIORITY
masks all interrupts including IPI's which map to a single
underlying priority. The fix does two things
1. It moves the setting of CPPR to after all IRQ migration
is complete
2. It sets the CPPR to LOWEST_PRIORITY, so that interrupts