Re: [kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-03-14 Thread Michael Ellerman
On Wed, 2017-02-22 at 04:43:59 UTC, Alexey Kardashevskiy wrote: > The IODA2 specification says that a 64 DMA address cannot use top 4 bits > (3 are reserved and one is a "TVE select"); bottom page_shift bits > cannot be used for multilevel table addressing either. > > The existing IODA2 table

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-03-05 Thread Alexey Kardashevskiy
On 06/03/17 14:36, Benjamin Herrenschmidt wrote: > On Mon, 2017-03-06 at 12:28 +1100, Alexey Kardashevskiy wrote: >> 8192*8192*8192*65536>>40 = 32768TB of addressable memory (but there is no >> good reason not to use huge pages); > > No, 39 bits is half a TB. That's not enough. Ah. My bad. 55

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-03-05 Thread Benjamin Herrenschmidt
On Mon, 2017-03-06 at 12:28 +1100, Alexey Kardashevskiy wrote: > 8192*8192*8192*65536>>40 = 32768TB of addressable memory (but there is no > good reason not to use huge pages); No, 39 bits is half a TB. That's not enough. > 8192*8192*8192*4096>>40 = 2048TB or addressable memory (even with 2 >

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-03-05 Thread Alexey Kardashevskiy
On 06/03/17 10:03, Benjamin Herrenschmidt wrote: > On Mon, 2017-02-27 at 22:00 +1100, Michael Ellerman wrote: >>> The alternative would be allocating TCE tables as big as PAGE_SIZE >>> but >>> only using parts of it but this would complicate a bit bits of code >>> responsible for overall amount of

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-03-05 Thread Benjamin Herrenschmidt
On Mon, 2017-02-27 at 22:00 +1100, Michael Ellerman wrote: > > The alternative would be allocating TCE tables as big as PAGE_SIZE > > but > > only using parts of it but this would complicate a bit bits of code > > responsible for overall amount of memory used for TCE table. > > > > Or

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-02-27 Thread Alexey Kardashevskiy
On 27/02/17 22:00, Michael Ellerman wrote: > Alexey Kardashevskiy writes: > >> The IODA2 specification says that a 64 DMA address cannot use top 4 bits >> (3 are reserved and one is a "TVE select"); bottom page_shift bits >> cannot be used for multilevel table addressing either.

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-02-27 Thread Michael Ellerman
Alexey Kardashevskiy writes: > The IODA2 specification says that a 64 DMA address cannot use top 4 bits > (3 are reserved and one is a "TVE select"); bottom page_shift bits > cannot be used for multilevel table addressing either. > > The existing IODA2 table allocation code

Re: [PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-02-26 Thread Gavin Shan
On Wed, Feb 22, 2017 at 03:43:59PM +1100, Alexey Kardashevskiy wrote: >The IODA2 specification says that a 64 DMA address cannot use top 4 bits >(3 are reserved and one is a "TVE select"); bottom page_shift bits >cannot be used for multilevel table addressing either. > >The existing IODA2 table

[PATCH kernel] powerpc/powernv/ioda2: Gracefully fail if too many TCE levels requested

2017-02-21 Thread Alexey Kardashevskiy
The IODA2 specification says that a 64 DMA address cannot use top 4 bits (3 are reserved and one is a "TVE select"); bottom page_shift bits cannot be used for multilevel table addressing either. The existing IODA2 table allocation code aligns the minimum TCE table size to PAGE_SIZE so in the case