+ u32 eisr, eimr;
+ int errint;
+ unsigned int cascade_irq;
+
+ eisr = fsl_mpic_err_read(mpic-err_regs, eisr_offset);
+ eimr = fsl_mpic_err_read(mpic-err_regs, eimr_offset);
+
+ if (!(eisr ~eimr))
+ return IRQ_NONE;
+
+ while (eisr) {
+
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 10, 2012 7:17 AM
To: Wood Scott-B07421
Cc: Sethi Varun-B16395; Hamciuc Bogdan-BHAMCIU1; linuxppc-
d...@lists.ozlabs.org
Subject: Re: [PATCH 3/3 v2] powerpc/mpic: FSL MPIC error interrupt
: [PATCH 3/3 v2] powerpc/mpic: FSL MPIC error interrupt
support.
On Jul 9, 2012, at 3:22 PM, Scott Wood wrote:
On 07/09/2012 02:03 PM, Kumar Gala wrote:
On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
+int mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum) {
Why can't we
On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
All SOC device error interrupts are muxed and delivered to the core as a
single
MPIC error interrupt. Currently all the device drivers requiring access to
device
errors have to register for the MPIC error interrupt as a shared interrupt.
On 07/09/2012 02:03 PM, Kumar Gala wrote:
On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
+int mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
+{
Why can't we do this during mpic_init() time?
Are you willing to hardcode that IRQ 16 is the error interrupt, without
waiting to
On Jul 9, 2012, at 3:22 PM, Scott Wood wrote:
On 07/09/2012 02:03 PM, Kumar Gala wrote:
On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
+int mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
+{
Why can't we do this during mpic_init() time?
Are you willing to hardcode that
